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Searched refs:ShiftOpc (Results 1 – 25 of 37) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h26 enum ShiftOpc { enum
44 static inline const char *getShiftOpcStr(ShiftOpc Op) { in getShiftOpcStr()
55 static inline unsigned getShiftOpcEncoding(ShiftOpc Op) { in getShiftOpcEncoding()
111 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc()
117 static inline ShiftOpc getSORegShOp(unsigned Op) { in getSORegShOp()
118 return (ShiftOpc)(Op & 7); in getSORegShOp()
406 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
418 static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { in getAM2ShiftOpc()
419 return (ShiftOpc)((AM2Opc >> 13) & 7); in getAM2ShiftOpc()
DARMMCCodeEmitter.cpp178 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
900 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
947 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue()
1101 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
1145 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getSORegImmOpValue()
1263 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getT2SORegOpValue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h27 enum ShiftOpc { enum
43 inline const char *getShiftOpcStr(ShiftOpc Op) { in getShiftOpcStr()
54 inline unsigned getShiftOpcEncoding(ShiftOpc Op) { in getShiftOpcEncoding()
110 inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc()
114 inline ShiftOpc getSORegShOp(unsigned Op) { return (ShiftOpc)(Op & 7); } in getSORegShOp()
397 inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
409 inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { in getAM2ShiftOpc()
410 return (ShiftOpc)((AM2Opc >> 13) & 7); in getAM2ShiftOpc()
DARMMCCodeEmitter.cpp219 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
1087 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1125 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue()
1340 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
1385 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getSORegImmOpValue()
1490 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getT2SORegOpValue()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAddressingModes.h27 enum ShiftOpc { enum
45 static inline const char *getShiftOpcStr(ShiftOpc Op) { in getShiftOpcStr()
56 static inline unsigned getShiftOpcEncoding(ShiftOpc Op) { in getShiftOpcEncoding()
112 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) { in getSORegOpc()
118 static inline ShiftOpc getSORegShOp(unsigned Op) { in getSORegShOp()
119 return (ShiftOpc)(Op & 7); in getSORegShOp()
407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
419 static inline ShiftOpc getAM2ShiftOpc(unsigned AM2Opc) { in getAM2ShiftOpc()
420 return (ShiftOpc)((AM2Opc >> 13) & 7); in getAM2ShiftOpc()
DARMMCCodeEmitter.cpp205 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { in getShiftOp()
1076 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm()); in getLdStSORegOpValue()
1114 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm); in getAddrMode2OffsetOpValue()
1329 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getSORegRegOpValue()
1374 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getSORegImmOpValue()
1479 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm()); in getT2SORegOpValue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
656 bool ARMInstructionSelector::selectShift(unsigned ShiftOpc, in selectShift() argument
659 MIB.addImm(ShiftOpc); in selectShift()
869 return selectShift(ARM_AM::ShiftOpc::lsr, MIB); in select()
871 return selectShift(ARM_AM::ShiftOpc::asr, MIB); in select()
873 return selectShift(ARM_AM::ShiftOpc::lsl, MIB); in select()
DARMSelectionDAGInfo.h24 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
DARMFastISel.cpp187 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2702 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; in ARMEmitIntExt()
2729 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; in ARMEmitIntExt()
2775 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
DARMISelDAGToDAG.cpp83 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
440 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
532 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
556 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectRegShifterOperand()
678 ARM_AM::ShiftOpc ShOpcVal = in SelectLdStSOReg()
758 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectAddrMode2OffsetReg()
1273 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg()
2330 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL); in tryV6T2BitfieldExtractOp()
DARMBaseInstrInfo.cpp198 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); in convertToThreeAddress()
603 ARM_AM::ShiftOpc ShiftOpc = ARM_AM::getAM2ShiftOpc(OffImm); in isLdstScaledRegNotPlusLsl2() local
604 if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled in isLdstScaledRegNotPlusLsl2()
605 bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2); in isLdstScaledRegNotPlusLsl2()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMSelectionDAGInfo.h23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
DARMISelDAGToDAG.cpp97 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
380 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
397 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
421 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectRegShifterOperand()
532 ARM_AM::ShiftOpc ShOpcVal = in SelectLdStSOReg()
672 ARM_AM::ShiftOpc ShOpcVal = in SelectAddrMode2Worker()
737 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectAddrMode2OffsetReg()
1159 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectT2ShifterOperandReg()
1294 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg()
DARMCodeEmitter.cpp927 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); in getMachineSoRegOpValue()
1453 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); in emitSaturateInstruction()
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.h24 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { in getShiftOpcForNode()
DARMISelDAGToDAG.cpp89 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
464 ARM_AM::ShiftOpc ShOpcVal, in isShifterOpProfitable()
554 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectImmShifterOperand()
578 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectRegShifterOperand()
692 ARM_AM::ShiftOpc ShOpcVal = in SelectLdStSOReg()
846 ARM_AM::ShiftOpc ShOpcVal = in SelectAddrMode2Worker()
912 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode()); in SelectAddrMode2OffsetReg()
1399 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode()); in SelectT2AddrModeSoReg()
2370 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL); in tryV6T2BitfieldExtractOp()
DARMFastISel.cpp156 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2676 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; in ARMEmitIntExt()
2703 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; in ARMEmitIntExt()
2747 ARM_AM::ShiftOpc ShiftTy) { in SelectShift()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
333 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
343 ARM_AM::ShiftOpc ShiftTy;
352 ARM_AM::ShiftOpc ShiftTy;
358 ARM_AM::ShiftOpc ShiftTy;
1505 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, in CreateShiftedRegister()
1520 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, in CreateShiftedImmediate()
1610 ARM_AM::ShiftOpc ShiftType, in CreateMem()
1629 ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
1869 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp763 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
801 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR)) in splitShift()
818 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR) in splitShift()
847 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR)) in splitShift()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp804 unsigned ShiftOpc = Left ? S2_asl_i_r in splitShift() local
842 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? LoR : TmpR)) in splitShift()
859 BuildMI(B, MI, DL, TII->get(ShiftOpc), HiR) in splitShift()
888 BuildMI(B, MI, DL, TII->get(ShiftOpc), (Left ? HiR : LoR)) in splitShift()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp249 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
266 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); in printSORegImmOperand()
830 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm()); in printT2SOOperand()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
515 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
525 ARM_AM::ShiftOpc ShiftTy;
535 ARM_AM::ShiftOpc ShiftTy;
542 ARM_AM::ShiftOpc ShiftTy;
2649 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedRegister()
2663 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedImmediate()
2804 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, in CreateMem()
2822 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
3098 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp389 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
749 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
759 ARM_AM::ShiftOpc ShiftTy;
769 ARM_AM::ShiftOpc ShiftTy;
776 ARM_AM::ShiftOpc ShiftTy;
2965 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedRegister()
2979 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, in CreateShiftedImmediate()
3120 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, in CreateMem()
3138 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, in CreatePostIdxReg()
3425 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) in tryParseShiftRegister()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp53 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
364 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp44 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, in printRegImmShift()
352 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm()); in printSORegRegOperand()

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