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Searched refs:getTargetExtractSubreg (Results 1 – 25 of 38) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp244 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32, in tryInlineAsm()
246 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm()
DSparcISelLowering.cpp2764 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
2766 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
2914 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS()
2916 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, in LowerFNEGorFABS()
/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp244 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32, in tryInlineAsm()
246 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm()
DSparcISelLowering.cpp2715 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
2717 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
2880 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS()
2882 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, in LowerFNEGorFABS()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp469 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, P); in createHvxPrefixPred()
472 return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, P); in createHvxPrefixPred()
710 VecV = DAG.getTargetExtractSubreg(SubIdx, dl, VecTy, VecV); in extractHvxSubvectorReg()
815 V0 = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, VecV); in insertHvxSubvectorReg()
816 V1 = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, VecV); in insertHvxSubvectorReg()
862 SDValue R0 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, V); in insertHvxSubvectorReg()
863 SDValue R1 = DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, V); in insertHvxSubvectorReg()
1320 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResTy, Pair); in LowerHvxMulh()
1323 return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResTy, Pair); in LowerHvxMulh()
DHexagonISelDAGToDAGHVX.cpp1011 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); in materialize()
1356 Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, Vec); in scalarizeShuffle()
1358 Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, Vec); in scalarizeShuffle()
DHexagonISelLowering.cpp2351 T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1); in extractVector()
2373 ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV); in extractVector()
2418 ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR); in insertVector()
2571 W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W); in LowerCONCAT_VECTORS()
DHexagonISelDAGToDAG.cpp523 Value = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo, in SelectIndexedStore()
799 SDValue E = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo, dl, ResTy, in SelectVAlign()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelDAGToDAG.cpp1930 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); in Select()
1938 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); in Select()
2078 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); in Select()
2086 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); in Select()
2144 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, in Select()
2173 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl, in Select()
2192 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, in Select()
2208 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl, in Select()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2277 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); in Select()
2286 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); in Select()
2474 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result); in Select()
2543 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, in Select()
2578 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl, in Select()
2603 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, in Select()
2626 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl, in Select()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp590 Value = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, in SelectIndexedStore()
1109 SDValue SubregHI = CurDAG->getTargetExtractSubreg(Hexagon::subreg_hireg, dl, in SelectBitOp()
1112 SDValue SubregLO = CurDAG->getTargetExtractSubreg(Hexagon::subreg_loreg, dl, in SelectBitOp()
DHexagonISelLowering.cpp2456 return DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::v2i16, in LowerBUILD_VECTOR()
2633 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec); in LowerEXTRACT_VECTOR()
2640 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N); in LowerEXTRACT_VECTOR()
2661 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N); in LowerEXTRACT_VECTOR()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1206 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1243 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1323 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy, in NarrowVector()
1356 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1408 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, in SelectPostLoadLane()
2868 SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT, in Select()
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1149 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1180 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1255 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy, in NarrowVector()
1288 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1340 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, in SelectPostLoadLane()
2657 SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT, in Select()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1937 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2207 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
2289 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg)); in SelectVLDDup()
4270 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm()
4272 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1874 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2152 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
2280 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg)); in SelectVLDDup()
4230 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm()
4232 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DSelectionDAG.h794 SDValue getTargetExtractSubreg(int SRIdx, DebugLoc DL, EVT VT,
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelDAGToDAG.cpp1669 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
1926 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
2003 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg)); in SelectVLDDup()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp2366 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result); in lowerGR128Binary()
2367 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result); in lowerGR128Binary()
2915 return DAG.getTargetExtractSubreg(SystemZ::subreg_r32, in lowerBITCAST()
2924 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL, in lowerBITCAST()
4905 SDValue Hi = DAG.getTargetExtractSubreg(SystemZ::subreg_h64, in lowerGR128ToI128()
4907 SDValue Lo = DAG.getTargetExtractSubreg(SystemZ::subreg_l64, in lowerGR128ToI128()
DSystemZISelDAGToDAG.cpp941 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); in convertTo()
/external/llvm/lib/Target/SystemZ/
DSystemZISelDAGToDAG.cpp917 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); in convertTo()
/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h1087 SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp3221 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result); in Select()
3307 Reg = CurDAG->getTargetExtractSubreg(SubRegOp, dl, VT, Reg); in Select()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DSelectionDAG.h1230 SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp1421 = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0)); in SelectATOMIC_CMP_SWAP()

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