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Searched refs:Pat (Results 1 – 25 of 399) sorted by relevance

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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepMapAsm2Intrin.td14 def: Pat<(int_hexagon_C2_cmpeq IntRegs:$src1, IntRegs:$src2),
16 def: Pat<(int_hexagon_C2_cmpgt IntRegs:$src1, IntRegs:$src2),
18 def: Pat<(int_hexagon_C2_cmpgtu IntRegs:$src1, IntRegs:$src2),
20 def: Pat<(int_hexagon_C2_cmpeqp DoubleRegs:$src1, DoubleRegs:$src2),
22 def: Pat<(int_hexagon_C2_cmpgtp DoubleRegs:$src1, DoubleRegs:$src2),
24 def: Pat<(int_hexagon_C2_cmpgtup DoubleRegs:$src1, DoubleRegs:$src2),
26 def: Pat<(int_hexagon_A4_rcmpeqi IntRegs:$src1, s32_0ImmPred_timm:$src2),
28 def: Pat<(int_hexagon_A4_rcmpneqi IntRegs:$src1, s32_0ImmPred_timm:$src2),
30 def: Pat<(int_hexagon_A4_rcmpeq IntRegs:$src1, IntRegs:$src2),
32 def: Pat<(int_hexagon_A4_rcmpneq IntRegs:$src1, IntRegs:$src2),
[all …]
DHexagonMapAsm2IntrinV65.gen.td9 def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), (A6_vcmpbeq_notany Dou…
10 def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat …
11 def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwu…
12 def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat …
13 def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhu…
14 def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubr…
15 def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasr…
16 def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX]>;
17 def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX…
18 def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, Use…
[all …]
DHexagonPatternsHVX.td100 def: Pat<(ResType (Load I32:$Rt)),
102 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
107 def: Pat<(ResType (Load (HexagonCP tconstpool:$A))),
109 def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$A))),
116 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
118 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
142 def: Pat<(Store Value:$Vs, I32:$Rt),
144 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
177 def: Pat<(VecI8 vzero), (V6_vd0)>;
178 def: Pat<(VecI16 vzero), (V6_vd0)>;
[all …]
DHexagonIntrinsics.td12 : Pat <(IntID I32:$Rs),
16 : Pat <(IntID I32:$Rs, I32:$Rt),
20 : Pat <(IntID I32:$Rs, I64:$Rt),
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
27 def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt),
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
32 def: Pat<(int_hexagon_A2_subri timm:$s10, IntRegs:$Rs),
34 def: Pat<(int_hexagon_A2_subp DoubleRegs:$Rs, DoubleRegs:$Rt),
37 def: Pat<(int_hexagon_M2_mpyi IntRegs:$Rs, IntRegs:$Rt),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepMapAsm2Intrin.td14 def: Pat<(int_hexagon_S2_asr_r_p_or DoubleRegs:$src1, DoubleRegs:$src2, IntRegs:$src3),
16 def: Pat<(int_hexagon_S2_vsatwh DoubleRegs:$src1),
18 def: Pat<(int_hexagon_M2_mpysu_up IntRegs:$src1, IntRegs:$src2),
20 def: Pat<(int_hexagon_M2_mpyud_acc_ll_s0 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
22 def: Pat<(int_hexagon_M2_mpyud_acc_ll_s1 DoubleRegs:$src1, IntRegs:$src2, IntRegs:$src3),
24 def: Pat<(int_hexagon_M2_cmpysc_s1 IntRegs:$src1, IntRegs:$src2),
26 def: Pat<(int_hexagon_M2_cmpysc_s0 IntRegs:$src1, IntRegs:$src2),
28 def: Pat<(int_hexagon_M4_cmpyi_whc DoubleRegs:$src1, IntRegs:$src2),
30 def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s1 IntRegs:$src1, IntRegs:$src2),
32 def: Pat<(int_hexagon_M2_mpy_sat_rnd_lh_s0 IntRegs:$src1, IntRegs:$src2),
[all …]
DHexagonMapAsm2IntrinV65.gen.td9 def: Pat<(int_hexagon_A6_vcmpbeq_notany DoubleRegs:$src1, DoubleRegs:$src2), (A6_vcmpbeq_notany Dou…
10 def: Pat<(int_hexagon_V6_vasruwuhsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwuhsat …
11 def: Pat<(int_hexagon_V6_vasruwuhsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruwu…
12 def: Pat<(int_hexagon_V6_vasruhubsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubsat …
13 def: Pat<(int_hexagon_V6_vasruhubsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhu…
14 def: Pat<(int_hexagon_V6_vasruhubrndsat HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasruhubr…
15 def: Pat<(int_hexagon_V6_vasruhubrndsat_128B HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3), (V6_vasr…
16 def: Pat<(int_hexagon_V6_vabsb HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX]>;
17 def: Pat<(int_hexagon_V6_vabsb_128B HvxVR:$src1), (V6_vabsb HvxVR:$src1)>, Requires<[HasV65, UseHVX…
18 def: Pat<(int_hexagon_V6_vabsb_sat HvxVR:$src1), (V6_vabsb_sat HvxVR:$src1)>, Requires<[HasV65, Use…
[all …]
DHexagonIntrinsics.td12 : Pat <(IntID I32:$Rs),
16 : Pat <(IntID I32:$Rs, I32:$Rt),
20 : Pat <(IntID I32:$Rs, I64:$Rt),
23 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
25 def: Pat<(int_hexagon_A2_addi IntRegs:$Rs, timm:$s16),
27 def: Pat<(int_hexagon_A2_addp DoubleRegs:$Rs, DoubleRegs:$Rt),
30 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
32 def: Pat<(int_hexagon_A2_subri timm:$s10, IntRegs:$Rs),
34 def: Pat<(int_hexagon_A2_subp DoubleRegs:$Rs, DoubleRegs:$Rt),
37 def: Pat<(int_hexagon_M2_mpyi IntRegs:$Rs, IntRegs:$Rt),
[all …]
DHexagonPatternsHVX.td99 def: Pat<(ResType (Load I32:$Rt)),
101 def: Pat<(ResType (Load (add I32:$Rt, ImmPred:$s))),
106 def: Pat<(ResType (Load (HexagonCP tconstpool:$A))),
108 def: Pat<(ResType (Load (HexagonAtPcrel tconstpool:$A))),
115 def: Pat<(ResType (Load (valignaddr I32:$Rt))),
117 def: Pat<(ResType (Load (add (valignaddr I32:$Rt), ImmPred:$Off))),
141 def: Pat<(Store Value:$Vs, I32:$Rt),
143 def: Pat<(Store Value:$Vs, (add I32:$Rt, ImmPred:$s)),
174 def: Pat<(VecI8 vzero), (V6_vd0)>;
175 def: Pat<(VecI16 vzero), (V6_vd0)>;
[all …]
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrMemory.td77 def : Pat<(i32 (load I32:$addr)), (LOAD_I32 0, $addr, 0)>;
78 def : Pat<(i64 (load I32:$addr)), (LOAD_I64 0, $addr, 0)>;
79 def : Pat<(f32 (load I32:$addr)), (LOAD_F32 0, $addr, 0)>;
80 def : Pat<(f64 (load I32:$addr)), (LOAD_F64 0, $addr, 0)>;
83 def : Pat<(i32 (load (regPlusImm I32:$addr, imm:$off))),
85 def : Pat<(i64 (load (regPlusImm I32:$addr, imm:$off))),
87 def : Pat<(f32 (load (regPlusImm I32:$addr, imm:$off))),
89 def : Pat<(f64 (load (regPlusImm I32:$addr, imm:$off))),
91 def : Pat<(i32 (load (or_is_add I32:$addr, imm:$off))),
93 def : Pat<(i64 (load (or_is_add I32:$addr, imm:$off))),
[all …]
/external/tensorflow/tensorflow/compiler/mlir/lite/transforms/
Dlegalize_patterns.td72 def LegalizeTFConstToTFLConst: Pat<(TF_ConstOp ElementsAttr:$value),
76 def ConvertTfConstToStdConst : Pat<
98 def LegalizeAbs : Pat<(TF_AbsOp $arg), (TFL_AbsOp $arg)>;
99 def LegalizeAddN : Pat<(TF_AddNOp $inputs), (TFL_AddNOp $inputs)>;
101 def LegalizeAveragePool : Pat<(TF_AvgPoolOp $value,
114 def LegalizeArgMax : Pat<(TF_ArgMaxOp $input, $dim),
116 def LegalizeArgMin : Pat<(TF_ArgMinOp $input, $dim),
119 def LegalizeBroadcastTo : Pat<(TF_BroadcastToOp $input, $dim),
122 def LegalizeCeil : Pat<(TF_CeilOp $arg), (TFL_CeilOp $arg)>;
124 def LegalizeCos : Pat<(TF_CosOp $arg), (TFL_CosOp $arg)>;
[all …]
/external/llvm-project/llvm/lib/Target/VE/
DVEInstrIntrinsicVL.gen.td1 def : Pat<(int_ve_vl_vld_vssl i64:$sy, i64:$sz, i32:$vl), (VLDrrl i64:$sy, i64:$sz, i32:$vl)>;
2 def : Pat<(int_ve_vl_vld_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDrrl_v i64:$sy, i64:$sz,…
3 def : Pat<(int_ve_vl_vld_vssl simm7:$I, i64:$sz, i32:$vl), (VLDirl (LO7 $I), i64:$sz, i32:$vl)>;
4 def : Pat<(int_ve_vl_vld_vssvl simm7:$I, i64:$sz, v256f64:$pt, i32:$vl), (VLDirl_v (LO7 $I), i64:$s…
5 def : Pat<(int_ve_vl_vldnc_vssl i64:$sy, i64:$sz, i32:$vl), (VLDNCrrl i64:$sy, i64:$sz, i32:$vl)>;
6 def : Pat<(int_ve_vl_vldnc_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDNCrrl_v i64:$sy, i64:…
7 def : Pat<(int_ve_vl_vldnc_vssl simm7:$I, i64:$sz, i32:$vl), (VLDNCirl (LO7 $I), i64:$sz, i32:$vl)>;
8 def : Pat<(int_ve_vl_vldnc_vssvl simm7:$I, i64:$sz, v256f64:$pt, i32:$vl), (VLDNCirl_v (LO7 $I), i6…
9 def : Pat<(int_ve_vl_vldu_vssl i64:$sy, i64:$sz, i32:$vl), (VLDUrrl i64:$sy, i64:$sz, i32:$vl)>;
10 def : Pat<(int_ve_vl_vldu_vssvl i64:$sy, i64:$sz, v256f64:$pt, i32:$vl), (VLDUrrl_v i64:$sy, i64:$s…
[all …]
/external/tensorflow/tensorflow/compiler/mlir/tosa/transforms/
Dtf_legalize_patterns.td25 def : Pat<(TF_ConstOp ElementsAttr : $value), (Tosa_ConstOp $value)>;
29 def : Pat<(TF_IdentityOp $value), (replaceWithValue $value)>;
30 def : Pat<(TF_AbsOp $arg), (Tosa_AbsOp $arg)>;
31 def : Pat<(TF_CeilOp $arg), (Tosa_CeilOp $arg)>;
32 def : Pat<(TF_FloorOp $arg), (Tosa_FloorOp $arg)>;
33 def : Pat<(TF_ExpOp $arg), (Tosa_ExpOp $arg)>;
34 def : Pat<(TF_LogOp $arg), (Tosa_LogOp $arg)>;
35 def : Pat<(TF_ReciprocalOp $arg), (Tosa_ReciprocalOp $arg)>;
36 def : Pat<(TF_RsqrtOp $arg), (Tosa_RsqrtOp $arg)>;
37 def : Pat<(TF_LogicalNotOp $arg), (Tosa_LogicalNotOp $arg)>;
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td17 def : Pat<(atomic_fence (i64 4), (imm)), (DMB (i32 0x9))>;
18 def : Pat<(atomic_fence (imm), (imm)), (DMB (i32 0xb))>;
44 def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
45 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
48 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
51 def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
54 def : Pat<(relaxed_load<atomic_load_8>
59 def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
60 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
63 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
[all …]
DAArch64InstrInfo.td372 def : Pat<(AArch64LOADgot tglobaltlsaddr:$addr),
375 def : Pat<(AArch64LOADgot texternalsym:$addr),
378 def : Pat<(AArch64LOADgot tconstpool:$addr),
424 def : Pat<(AArch64threadpointer), (MRS 0xde82)>;
428 def : Pat<(readcyclecounter), (MRS 0xdce8)>;
548 def : Pat<(i64 i64imm_32bit:$src),
563 def : Pat<(f32 fpimm:$in),
565 def : Pat<(f64 fpimm:$in),
571 def : Pat<(AArch64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
578 def : Pat<(AArch64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td987 def : Pat<(v4i32 (vnot_ppc v4i32:$A)),
989 def : Pat<(v4i32 (or (and (vnot_ppc v4i32:$C), v4i32:$A),
994 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
997 def : Pat<(f64 (extractelt v2f64:$S, 0)),
999 def : Pat<(f64 (extractelt v2f64:$S, 1)),
1004 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
1008 def : Pat<(f64 (extractelt v2f64:$S, 0)),
1010 def : Pat<(f64 (extractelt v2f64:$S, 1)),
1015 def : Pat<(fma (fneg f64:$A), f64:$B, f64:$C),
1017 def : Pat<(fma f64:$A, (fneg f64:$B), f64:$C),
[all …]
DPPCInstrHTM.td97 def : Pat<(int_ppc_tbegin i32:$R),
100 def : Pat<(int_ppc_tend i32:$R),
103 def : Pat<(int_ppc_tabort i32:$R),
106 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
109 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
112 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
115 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
118 def : Pat<(int_ppc_tcheck),
121 def : Pat<(int_ppc_treclaim i32:$RA),
124 def : Pat<(int_ppc_trechkpt),
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td19 def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>;
20 def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>;
46 def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
47 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
50 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
53 def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
56 def : Pat<(relaxed_load<atomic_load_8>
61 def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
62 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
65 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstrAtomics.td19 def : Pat<(atomic_fence (i64 4), (timm)), (DMB (i32 0x9))>;
20 def : Pat<(atomic_fence (timm), (timm)), (DMB (i32 0xb))>;
46 def : Pat<(acquiring_load<atomic_load_8> GPR64sp:$ptr), (LDARB GPR64sp:$ptr)>;
47 def : Pat<(relaxed_load<atomic_load_8> (ro_Windexed8 GPR64sp:$Rn, GPR32:$Rm,
50 def : Pat<(relaxed_load<atomic_load_8> (ro_Xindexed8 GPR64sp:$Rn, GPR64:$Rm,
53 def : Pat<(relaxed_load<atomic_load_8> (am_indexed8 GPR64sp:$Rn,
56 def : Pat<(relaxed_load<atomic_load_8>
61 def : Pat<(acquiring_load<atomic_load_16> GPR64sp:$ptr), (LDARH GPR64sp:$ptr)>;
62 def : Pat<(relaxed_load<atomic_load_16> (ro_Windexed16 GPR64sp:$Rn, GPR32:$Rm,
65 def : Pat<(relaxed_load<atomic_load_16> (ro_Xindexed16 GPR64sp:$Rn, GPR64:$Rm,
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrVecCompiler.td10 // compiler, as well as Pat patterns used during instruction selection.
20 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
22 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
28 def : Pat<(f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
30 def : Pat<(f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
36 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
39 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
45 def : Pat<(v4f32 (scalar_to_vector FR32X:$src)),
48 def : Pat<(v2f64 (scalar_to_vector FR64X:$src)),
60 def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
[all …]
DX86InstrCompiler.td10 // as well as Pat patterns used during instruction selection.
48 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
66 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
284 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
285 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
286 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>;
303 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
304 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
329 def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>;
334 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td10 // compiler, as well as Pat patterns used during instruction selection.
20 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
22 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
28 def : Pat<(f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
30 def : Pat<(f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
36 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
39 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
45 def : Pat<(v4f32 (scalar_to_vector FR32X:$src)),
48 def : Pat<(v2f64 (scalar_to_vector FR64X:$src)),
60 def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
[all …]
DX86InstrCompiler.td10 // as well as Pat patterns used during instruction selection.
48 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
66 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
274 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
275 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
276 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>;
293 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
294 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
320 def : Pat<(i64 mov64imm32:$src), (MOV32ri64 mov64imm32:$src)>;
324 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrHTM.td96 def : Pat<(int_ppc_tbegin i32:$R),
102 def : Pat<(int_ppc_tend i32:$R),
106 def : Pat<(int_ppc_tabort i32:$R),
109 def : Pat<(int_ppc_tabortwc i32:$TO, i32:$RA, i32:$RB),
112 def : Pat<(int_ppc_tabortwci i32:$TO, i32:$RA, i32:$SI),
115 def : Pat<(int_ppc_tabortdc i32:$TO, i32:$RA, i32:$RB),
118 def : Pat<(int_ppc_tabortdci i32:$TO, i32:$RA, i32:$SI),
121 def : Pat<(int_ppc_tcheck),
124 def : Pat<(int_ppc_treclaim i32:$RA),
127 def : Pat<(int_ppc_trechkpt),
[all …]
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td294 def : Pat<(Ty (scalar_to_vector In)), (Ty NonPermOut)>;
295 def : Pat<(Ty (PPCSToV In)), (Ty PermOut)>;
2440 def : Pat<(v4i32 (vnot_ppc v4i32:$A)),
2442 def : Pat<(v4i32 (or (and (vnot_ppc v4i32:$C), v4i32:$A),
2447 def : Pat<(PPCfnmsub f64:$A, f64:$B, f64:$C),
2449 def : Pat<(fneg (PPCfnmsub f64:$A, f64:$B, f64:$C)),
2451 def : Pat<(PPCfnmsub f64:$A, f64:$B, (fneg f64:$C)),
2454 def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C),
2456 def : Pat<(fneg (PPCfnmsub v2f64:$A, v2f64:$B, v2f64:$C)),
2458 def : Pat<(PPCfnmsub v2f64:$A, v2f64:$B, (fneg v2f64:$C)),
[all …]
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/transforms/
Dcanonicalize.td41 def AddToAddV2 : Pat<(TF_AddOp TF_NumberTensor:$arg0, TF_NumberTensor:$arg1),
48 def AddV2OfNegLeft : Pat<(TF_AddV2Op (TF_NegOp $arg0), $arg1),
51 def AddV2OfNegRight : Pat<(TF_AddV2Op $arg0, (TF_NegOp $arg1)),
64 Pat<(TF_BatchMatMulOp AnyStaticShapeTensor:$x, AnyStaticShapeTensor:$y,
68 def BatchMatMulToMatMul : Pat<(TF_BatchMatMulOp $x, $y, $adj_x, $adj_y),
76 def BatchMatMulV2ToMatMul : Pat<(TF_BatchMatMulV2Op $x, $y, $adj_x, $adj_y),
89 Pat<(TF_BatchToSpaceOp $input, $crops, $block_size),
99 def BiasAddV1ToBiasAdd : Pat<(TF_BiasAddV1Op $arg0, $arg1),
106 def BitcastSameType : Pat<(TF_BitcastOp:$res $arg), (replaceWithValue $arg),
110 def BitcastNested : Pat<(TF_BitcastOp (TF_BitcastOp $arg)),
[all …]

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