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Searched refs:displacement (Results 1 – 21 of 21) sorted by relevance

/art/compiler/dex/quick/mips/
Dutility_mips.cc455 LIR* MipsMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, in LoadBaseDispBody() argument
469 bool short_form = IS_SIMM16(displacement); in LoadBaseDispBody()
486 short_form = IS_SIMM16_2WORD(displacement); in LoadBaseDispBody()
487 DCHECK_EQ((displacement & 0x3), 0); in LoadBaseDispBody()
497 DCHECK_EQ((displacement & 0x3), 0); in LoadBaseDispBody()
501 DCHECK_EQ((displacement & 0x1), 0); in LoadBaseDispBody()
505 DCHECK_EQ((displacement & 0x1), 0); in LoadBaseDispBody()
519 load = res = NewLIR3(opcode, r_dest.GetReg(), displacement, r_base.GetReg()); in LoadBaseDispBody()
521 … load = res = NewLIR3(opcode, r_dest.GetLowReg(), displacement + LOWORD_OFFSET, r_base.GetReg()); in LoadBaseDispBody()
522 load2 = NewLIR3(opcode, r_dest.GetHighReg(), displacement + HIWORD_OFFSET, r_base.GetReg()); in LoadBaseDispBody()
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Dcodegen_mips.h35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
45 LIR* GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest);
46 LIR* GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src);
162 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest,
165 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src,
Dtarget_mips.cc495 LIR* MipsMir2Lir::GenAtomic64Load(RegStorage r_base, int displacement, RegStorage r_dest) { in GenAtomic64Load() argument
501 OpRegRegImm(kOpAdd, reg_ptr, r_base, displacement); in GenAtomic64Load()
509 LIR* MipsMir2Lir::GenAtomic64Store(RegStorage r_base, int displacement, RegStorage r_src) { in GenAtomic64Store() argument
515 OpRegRegImm(kOpAdd, temp_ptr, r_base, displacement); in GenAtomic64Store()
DREADME.mips47 slot and adjust the displacement. However, given that code expansion is
/art/compiler/dex/quick/arm/
Dutility_arm.cc825 int displacement, RegStorage r_src_dest, in LoadStoreUsingInsnWithOffsetImm8Shl2() argument
827 DCHECK_EQ(displacement & 3, 0); in LoadStoreUsingInsnWithOffsetImm8Shl2()
829 int encoded_disp = (displacement & kOffsetMask) >> 2; // Within range of the instruction. in LoadStoreUsingInsnWithOffsetImm8Shl2()
831 if ((displacement & ~kOffsetMask) != 0) { in LoadStoreUsingInsnWithOffsetImm8Shl2()
834 OpRegRegImm(kOpAdd, r_ptr, r_base, displacement & ~kOffsetMask); in LoadStoreUsingInsnWithOffsetImm8Shl2()
843 if ((displacement & ~kOffsetMask) != 0 && !r_work.Valid()) { in LoadStoreUsingInsnWithOffsetImm8Shl2()
854 LIR* ArmMir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, in LoadBaseDispBody() argument
859 bool thumb2Form = (displacement < 4092 && displacement >= 0); in LoadBaseDispBody()
861 int encoded_disp = displacement; in LoadBaseDispBody()
869 load = LoadStoreUsingInsnWithOffsetImm8Shl2(kThumb2Vldrd, r_base, displacement, r_dest); in LoadBaseDispBody()
[all …]
Dcodegen_arm.h35 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
41 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
164 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size);
165 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
198 int displacement, RegStorage r_src_dest,
/art/compiler/dex/quick/x86/
Dutility_x86.cc394 int displacement = SRegOffset(rl_dest.s_reg_low); in OpMemReg() local
412 LIR *l = NewLIR3(opcode, rs_rX86_SP.GetReg(), displacement, r_value); in OpMemReg()
414 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); in OpMemReg()
415 AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is64Bit /* is_64bit */); in OpMemReg()
423 int displacement = SRegOffset(rl_value.s_reg_low); in OpRegMem() local
438 LIR *l = NewLIR3(opcode, r_dest.GetReg(), rs_rX86_SP.GetReg(), displacement); in OpRegMem()
440 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is64Bit /* is_64bit */); in OpRegMem()
635 int displacement, RegStorage r_dest, OpSize size) { in LoadBaseIndexedDisp() argument
653 DCHECK_EQ((displacement & 0x3), 0); in LoadBaseIndexedDisp()
670 DCHECK_EQ((displacement & 0x3), 0); in LoadBaseIndexedDisp()
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Dint_x86.cc1275 void X86Mir2Lir::GenImulMemImm(RegStorage dest, int sreg, int displacement, int val) { in GenImulMemImm() argument
1285 LoadBaseDisp(rs_rX86_SP, displacement, dest, k32, kNotVolatile); in GenImulMemImm()
1289 rs_rX86_SP.GetReg(), displacement, val); in GenImulMemImm()
1290 AnnotateDalvikRegAccess(m, displacement >> 2, true /* is_load */, true /* is_64bit */); in GenImulMemImm()
1408 int displacement = SRegOffset(rl_src1.s_reg_low); in GenMulLongConst() local
1416 GenImulMemImm(rs_r1, GetSRegHi(rl_src1.s_reg_low), displacement + HIWORD_OFFSET, val_lo); in GenMulLongConst()
1417 GenImulMemImm(rs_r0, rl_src1.s_reg_low, displacement + LOWORD_OFFSET, val_hi); in GenMulLongConst()
1430 LIR *m = NewLIR2(kX86Mul32DaM, rs_rX86_SP.GetReg(), displacement + LOWORD_OFFSET); in GenMulLongConst()
1431 AnnotateDalvikRegAccess(m, (displacement + LOWORD_OFFSET) >> 2, in GenMulLongConst()
1511 int displacement = SRegOffset(rl_src2.s_reg_low); in GenMulLong() local
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Dfp_x86.cc160 int displacement = is_double ? dest_v_reg_offset + LOWORD_OFFSET : dest_v_reg_offset; in GenLongToFP() local
161 LIR *fstp = NewLIR2NoDest(opcode, rs_rX86_SP.GetReg(), displacement); in GenLongToFP()
162 AnnotateDalvikRegAccess(fstp, displacement >> 2, false /* is_load */, is_double); in GenLongToFP()
418 int displacement = dest_v_reg_offset + LOWORD_OFFSET; in GenRemFP() local
420 LIR *fst = NewLIR2NoDest(opcode, rs_rX86_SP.GetReg(), displacement); in GenRemFP()
421 AnnotateDalvikRegAccess(fst, displacement >> 2, false /* is_load */, is_double /* is64bit */); in GenRemFP()
628 int displacement = SRegOffset(rl_dest.s_reg_low); in GenInlinedAbsFloat() local
630 LIR *lir = NewLIR3(kX86And32MI, rs_rX86_SP.GetReg(), displacement, 0x7fffffff); in GenInlinedAbsFloat()
631 AnnotateDalvikRegAccess(lir, displacement >> 2, false /*is_load */, false /* is_64bit */); in GenInlinedAbsFloat()
632 AnnotateDalvikRegAccess(lir, displacement >> 2, true /* is_load */, false /* is_64bit*/); in GenInlinedAbsFloat()
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Dcodegen_x86.h72 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
78 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src,
410 LIR* LoadBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
412 LIR* StoreBaseIndexedDisp(RegStorage r_base, RegStorage r_index, int scale, int displacement,
422 int32_t raw_base, int32_t displacement);
767 void GenImulMemImm(RegStorage dest, int sreg, int displacement, int val);
Dcall_x86.cc292 int displacement = SRegOffset(base_of_code_->s_reg_low); in GenEntrySequence() local
294 setup_method_address_[1] = StoreBaseDisp(rs_rX86_SP, displacement, method_start, in GenEntrySequence()
Dtarget_x86.cc917 int displacement = SRegOffset(rl_dest.s_reg_low); in GenConstWide() local
920 LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); in GenConstWide()
921 AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, in GenConstWide()
923 store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); in GenConstWide()
924 AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, in GenConstWide()
1359 int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); in GenInlinedIndexOf() local
1361 Load32Disp(rs_rX86_SP, displacement, rs_rDI); in GenInlinedIndexOf()
2268 int displacement = SRegOffset(rl_result.s_reg_low); in GenReduceVector() local
2269 LIR *l = NewLIR3(extr_opcode, rs_rX86_SP.GetReg(), displacement, rs_src1.GetReg()); in GenReduceVector()
2270 AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is_wide /* is_64bit */); in GenReduceVector()
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Dassemble_x86.cc613 int32_t raw_base, int32_t displacement) { in ComputeSize() argument
663 if (displacement != 0 || LowRegisterBits(raw_base) == rs_rBP.GetRegNum()) { in ComputeSize()
668 size += IS_SIMM8(displacement) ? 1 : 4; in ComputeSize()
1325 int32_t displacement, int32_t raw_cl) { in EmitShiftMemCl() argument
1334 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, displacement); in EmitShiftMemCl()
/art/compiler/dex/quick/arm64/
Dutility_arm64.cc1197 LIR* Arm64Mir2Lir::LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, in LoadBaseDispBody() argument
1249 bool displacement_is_aligned = (displacement & ((1 << scale) - 1)) == 0; in LoadBaseDispBody()
1250 int scaled_disp = displacement >> scale; in LoadBaseDispBody()
1254 } else if (alt_opcode != kA64Brk1d && IS_SIGNED_IMM9(displacement)) { in LoadBaseDispBody()
1256 load = NewLIR3(alt_opcode, r_dest.GetReg(), r_base.GetReg(), displacement); in LoadBaseDispBody()
1261 LoadConstantWide(r_scratch, displacement); in LoadBaseDispBody()
1269 AnnotateDalvikRegAccess(load, displacement >> 2, true /* is_load */, r_dest.Is64Bit()); in LoadBaseDispBody()
1274 LIR* Arm64Mir2Lir::LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, in LoadBaseDisp() argument
1279 LIR* load = LoadBaseDispBody(r_base, displacement, r_dest, size); in LoadBaseDisp()
1289 LIR* Arm64Mir2Lir::LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, in LoadRefDisp() argument
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Dcodegen_arm64.h75 LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest,
77 LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest,
85 LIR* StoreBaseDisp(RegStorage r_base, int displacement, RegStorage r_src, OpSize size,
87 LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, VolatileKind is_volatile)
379 LIR* LoadBaseDispBody(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size);
380 LIR* StoreBaseDispBody(RegStorage r_base, int displacement, RegStorage r_src, OpSize size);
/art/compiler/utils/x86_64/
Dassembler_x86_64_test.cc265 ssize_t displacement = static_cast<ssize_t>(frame_size) - (spill_regs.size() * 8 + 8); in buildframe_test_fn() local
266 str << "subq $" << displacement << ", %rsp\n"; in buildframe_test_fn()
295 ssize_t displacement = static_cast<ssize_t>(frame_size) - spill_regs.size() * 8 - 8; in removeframe_test_fn() local
296 str << "addq $" << displacement << ", %rsp\n"; in removeframe_test_fn()
/art/compiler/dex/quick/
Dmir_to_lir.h995 virtual LIR* LoadWordDisp(RegStorage r_base, int displacement, RegStorage r_dest) { in LoadWordDisp() argument
996 return LoadBaseDisp(r_base, displacement, r_dest, kWord, kNotVolatile); in LoadWordDisp()
999 virtual LIR* Load32Disp(RegStorage r_base, int displacement, RegStorage r_dest) { in Load32Disp() argument
1000 return LoadBaseDisp(r_base, displacement, r_dest, k32, kNotVolatile); in Load32Disp()
1003 virtual LIR* LoadRefDisp(RegStorage r_base, int displacement, RegStorage r_dest, in LoadRefDisp() argument
1005 return LoadBaseDisp(r_base, displacement, r_dest, kReference, is_volatile); in LoadRefDisp()
1027 virtual LIR* StoreWordDisp(RegStorage r_base, int displacement, RegStorage r_src) { in StoreWordDisp() argument
1028 return StoreBaseDisp(r_base, displacement, r_src, kWord, kNotVolatile); in StoreWordDisp()
1031 virtual LIR* StoreRefDisp(RegStorage r_base, int displacement, RegStorage r_src, in StoreRefDisp() argument
1033 return StoreBaseDisp(r_base, displacement, r_src, kReference, is_volatile); in StoreRefDisp()
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/art/compiler/jni/quick/
Dcalling_convention.h60 void ResetIterator(FrameOffset displacement) { in ResetIterator() argument
61 displacement_ = displacement; in ResetIterator()
/art/disassembler/
Ddisassembler_x86.cc1221 int32_t displacement; in DumpInstruction() local
1223 displacement = *reinterpret_cast<const int8_t*>(instr); in DumpInstruction()
1227 displacement = *reinterpret_cast<const int32_t*>(instr); in DumpInstruction()
1230 args << StringPrintf("%+d (", displacement) in DumpInstruction()
1231 << FormatInstructionPointer(instr + displacement) in DumpInstruction()
/art/runtime/interpreter/
Dinterpreter_goto_table_impl.cc2407 int32_t displacement = static_cast<int32_t>(found_dex_pc) - static_cast<int32_t>(dex_pc); in ExecuteGotoImpl() local
2408 ADVANCE(displacement); in ExecuteGotoImpl()
Dinterpreter_switch_impl.cc34 int32_t displacement = static_cast<int32_t>(found_dex_pc) - static_cast<int32_t>(dex_pc); \
35 inst = inst->RelativeAt(displacement); \