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Searched refs:op (Results 1 – 25 of 31) sorted by relevance

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/art/compiler/dex/quick/mips/
Dfp_mips.cc26 int op = kMipsNop; in GenArithOpFloat() local
36 op = kMipsFadds; in GenArithOpFloat()
40 op = kMipsFsubs; in GenArithOpFloat()
44 op = kMipsFdivs; in GenArithOpFloat()
48 op = kMipsFmuls; in GenArithOpFloat()
66 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpFloat()
72 int op = kMipsNop; in GenArithOpDouble() local
78 op = kMipsFaddd; in GenArithOpDouble()
82 op = kMipsFsubd; in GenArithOpDouble()
86 op = kMipsFdivd; in GenArithOpDouble()
[all …]
Dutility_mips.cc116 LIR* MipsMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg() argument
118 switch (op) { in OpReg()
131 LIR* MipsMir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm() argument
137 switch (op) { in OpRegImm()
139 return OpRegRegImm(op, r_dest_src1, r_dest_src1, value); in OpRegImm()
142 return OpRegRegImm(op, r_dest_src1, r_dest_src1, value); in OpRegImm()
153 if (op == kOpCmp) in OpRegImm()
161 LIR* MipsMir2Lir::OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) { in OpRegRegReg() argument
163 switch (op) { in OpRegRegReg()
202 LIR* MipsMir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) { in OpRegRegImm() argument
[all …]
Dcodegen_mips.h144 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
146 LIR* OpReg(OpKind op, RegStorage r_dest_src);
149 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
150 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
153 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
154 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
155 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
182 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
/art/compiler/dex/quick/arm64/
Dfp_arm64.cc26 int op = kA64Brk1d; in GenArithOpFloat() local
32 op = kA64Fadd3fff; in GenArithOpFloat()
36 op = kA64Fsub3fff; in GenArithOpFloat()
40 op = kA64Fdiv3fff; in GenArithOpFloat()
44 op = kA64Fmul3fff; in GenArithOpFloat()
62 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpFloat()
68 int op = kA64Brk1d; in GenArithOpDouble() local
74 op = kA64Fadd3fff; in GenArithOpDouble()
78 op = kA64Fsub3fff; in GenArithOpDouble()
82 op = kA64Fdiv3fff; in GenArithOpDouble()
[all …]
Dutility_arm64.cc489 ArmOpcode op; in LoadConstantWide() local
495 op = WIDE(kA64Movn3rdM); in LoadConstantWide()
498 op = WIDE(kA64Movz3rdM); in LoadConstantWide()
507 res = NewLIR3(op, r_dest.GetReg(), halfword ^ background, shift); in LoadConstantWide()
550 LIR* Arm64Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg() argument
552 switch (op) { in OpReg()
561 LOG(FATAL) << "Bad opcode " << op; in OpReg()
566 LIR* Arm64Mir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift) { in OpRegRegShift() argument
571 switch (op) { in OpRegRegShift()
616 return OpRegRegRegShift(op, r_dest_src1, r_dest_src1, r_src2, shift); in OpRegRegShift()
[all …]
Dcodegen_arm64.h212 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
214 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
217 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
218 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
221 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
222 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value) OVERRIDE;
223 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2) OVERRIDE;
260 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
362 void GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2);
364 LIR* OpRegImm64(OpKind op, RegStorage r_dest_src1, int64_t value);
[all …]
Darm64_lir.h374 #define WIDE(op) ((ArmOpcode)((op) | kA64Wide)) argument
375 #define UNWIDE(op) ((ArmOpcode)((op) & ~kA64Wide)) argument
378 #define IS_WIDE(op) (((op) & kA64Wide) != 0) argument
Dint_arm64.cc65 OpKind op = kOpBkpt; in GenShiftOpLong() local
69 op = kOpLsl; in GenShiftOpLong()
73 op = kOpAsr; in GenShiftOpLong()
77 op = kOpLsr; in GenShiftOpLong()
85 OpRegRegReg(op, rl_result.reg, rl_src1.reg, As64BitReg(rl_shift.reg)); in GenShiftOpLong()
1021 void Arm64Mir2Lir::GenLongOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1, in GenLongOp() argument
1028 OpRegRegRegShift(op, rl_result.reg, rl_src1.reg, rl_src2.reg, ENCODE_NO_SHIFT); in GenLongOp()
1297 OpKind op = kOpBkpt; in GenShiftImmOpLong() local
1310 op = kOpLsl; in GenShiftImmOpLong()
1314 op = kOpAsr; in GenShiftImmOpLong()
[all …]
/art/compiler/dex/quick/x86/
Dutility_x86.cc120 LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg() argument
122 switch (op) { in OpReg()
128 LOG(FATAL) << "Bad case in OpReg " << op; in OpReg()
133 LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm() argument
138 switch (op) { in OpRegImm()
146 LOG(FATAL) << "Bad case in OpRegImm (64-bit) " << op; in OpRegImm()
149 switch (op) { in OpRegImm()
189 LOG(FATAL) << "Bad case in OpRegImm " << op; in OpRegImm()
195 LIR* X86Mir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg() argument
199 switch (op) { in OpRegReg()
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Dint_x86.cc1583 Instruction::Code op) { in GenLongRegOrMemOp() argument
1585 X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); in GenLongRegOrMemOp()
1601 x86op = GetOpcode(op, rl_dest, rl_src, true); in GenLongRegOrMemOp()
1620 x86op = GetOpcode(op, rl_dest, rl_src, true); in GenLongRegOrMemOp()
1627 void X86Mir2Lir::GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op) { in GenLongArith() argument
1634 GenLongRegOrMemOp(rl_result, rl_src, op); in GenLongArith()
1645 X86OpCode x86op = GetOpcode(op, rl_dest, rl_src, false); in GenLongArith()
1657 x86op = GetOpcode(op, rl_dest, rl_src, true); in GenLongArith()
1677 RegLocation rl_src2, Instruction::Code op, in GenLongArith() argument
1680 switch (op) { in GenLongArith()
[all …]
Dcodegen_x86.h188 bool GenLongImm(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
199 Instruction::Code op);
209 Instruction::Code op, bool is_commutative);
217 void GenLongArith(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
225 virtual void GenLongRegOrMemOp(RegLocation rl_dest, RegLocation rl_src, Instruction::Code op);
271 LIR* OpMem(OpKind op, RegStorage r_base, int disp) OVERRIDE;
273 LIR* OpReg(OpKind op, RegStorage r_dest_src) OVERRIDE;
276 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value) OVERRIDE;
277 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) OVERRIDE;
280 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
[all …]
Dfp_x86.cc26 X86OpCode op = kX86Nop; in GenArithOpFloat() local
36 op = kX86AddssRR; in GenArithOpFloat()
40 op = kX86SubssRR; in GenArithOpFloat()
44 op = kX86DivssRR; in GenArithOpFloat()
48 op = kX86MulssRR; in GenArithOpFloat()
71 NewLIR2(op, r_dest.GetReg(), r_src2.GetReg()); in GenArithOpFloat()
83 X86OpCode op = kX86Nop; in GenArithOpDouble() local
89 op = kX86AddsdRR; in GenArithOpDouble()
93 op = kX86SubsdRR; in GenArithOpDouble()
97 op = kX86DivsdRR; in GenArithOpDouble()
[all …]
/art/compiler/dex/quick/arm/
Dfp_arm.cc25 int op = kThumbBkpt; in GenArithOpFloat() local
35 op = kThumb2Vadds; in GenArithOpFloat()
39 op = kThumb2Vsubs; in GenArithOpFloat()
43 op = kThumb2Vdivs; in GenArithOpFloat()
47 op = kThumb2Vmuls; in GenArithOpFloat()
65 NewLIR3(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); in GenArithOpFloat()
71 int op = kThumbBkpt; in GenArithOpDouble() local
77 op = kThumb2Vaddd; in GenArithOpDouble()
81 op = kThumb2Vsubd; in GenArithOpDouble()
85 op = kThumb2Vdivd; in GenArithOpDouble()
[all …]
Dcodegen_arm.h147 LIR* OpMem(OpKind op, RegStorage r_base, int disp);
149 LIR* OpReg(OpKind op, RegStorage r_dest_src);
152 LIR* OpRegImm(OpKind op, RegStorage r_dest_src1, int value);
153 LIR* OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2);
156 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
157 LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value);
158 LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2);
166 LIR* OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2,
168 LIR* OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, int shift);
187 LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
[all …]
Dutility_arm.cc223 LIR* ArmMir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg() argument
225 switch (op) { in OpReg()
233 LOG(FATAL) << "Bad opcode " << op; in OpReg()
238 LIR* ArmMir2Lir::OpRegRegShift(OpKind op, RegStorage r_dest_src1, RegStorage r_src2, in OpRegRegShift() argument
243 switch (op) { in OpRegRegShift()
351 LOG(FATAL) << "Bad opcode: " << op; in OpRegRegShift()
371 LIR* ArmMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) { in OpRegReg() argument
372 return OpRegRegShift(op, r_dest_src1, r_src2, 0); in OpRegReg()
385 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg() argument
390 LIR* ArmMir2Lir::OpRegRegRegShift(OpKind op, RegStorage r_dest, RegStorage r_src1, in OpRegRegRegShift() argument
[all …]
Dint_arm.cc552 bool ArmMir2Lir::GetEasyMultiplyOp(int lit, ArmMir2Lir::EasyMultiplyOp* op) { in GetEasyMultiplyOp() argument
557 op->op = kOpInvalid; in GetEasyMultiplyOp()
562 op->op = kOpLsl; in GetEasyMultiplyOp()
563 op->shift = LowestSetBit(lit); in GetEasyMultiplyOp()
568 op->op = kOpAdd; in GetEasyMultiplyOp()
569 op->shift = LowestSetBit(lit - 1); in GetEasyMultiplyOp()
574 op->op = kOpRsub; in GetEasyMultiplyOp()
575 op->shift = LowestSetBit(lit + 1); in GetEasyMultiplyOp()
579 op->op = kOpInvalid; in GetEasyMultiplyOp()
580 op->shift = 0; in GetEasyMultiplyOp()
[all …]
/art/test/004-ThreadStress/src/
DMain.java71 for (Operation op : Operation.values()) { in main()
72 operationCount += op.frequency; in main()
87 for (Operation op : Operation.values()) { in main()
88 for (int f = 0; f < op.frequency; f++) { in main()
92 operations[o] = op; in main()
118 for (Operation op : Operation.values()) { in main()
119 System.out.println(op + " = " + distribution.get(op)); in main()
/art/disassembler/
Ddisassembler_arm.cc269 uint32_t op = (instruction >> 21) & 0xf; in DumpArm() local
270 opcode = kDataProcessingOperations[op]; in DumpArm()
271 bool implicit_s = ((op & ~3) == 8); // TST, TEQ, CMP, and CMN. in DumpArm()
272 bool is_mov = op == 0b1101 || op == 0b1111; in DumpArm()
400 uint64_t AdvSIMDExpand(uint32_t op, uint32_t cmode, uint32_t imm8) { in AdvSIMDExpand() argument
401 CHECK_EQ(op & 1, op); in AdvSIMDExpand()
421 if ((cmode & 1) == 0 && op == 0) { in AdvSIMDExpand()
424 } else if ((cmode & 1) == 0 && op != 0) { in AdvSIMDExpand()
430 } else if ((cmode & 1) != 0 && op == 0) { in AdvSIMDExpand()
473 uint32_t op = (instr >> 23) & 3; in DumpThumb32() local
[all …]
Ddisassembler_mips.cc183 uint32_t op = (instruction >> 26) & 0x3f; in Dump() local
185 opcode = StringPrintf("op=%d fn=%d", op, function); in Dump()
/art/compiler/dex/
Dglobal_value_numbering.h79 static uint64_t BuildKey(uint16_t op, uint16_t operand1, uint16_t operand2, uint16_t modifier) { in BuildKey() argument
80 return (static_cast<uint64_t>(op) << 48 | static_cast<uint64_t>(operand1) << 32 | in BuildKey()
85 uint16_t LookupValue(uint16_t op, uint16_t operand1, uint16_t operand2, uint16_t modifier) { in LookupValue() argument
87 uint64_t key = BuildKey(op, operand1, operand2, modifier); in LookupValue()
99 bool HasValue(uint16_t op, uint16_t operand1, uint16_t operand2, uint16_t modifier, in HasValue() argument
105 uint64_t key = BuildKey(op, operand1, operand2, modifier); in HasValue()
/art/compiler/dex/quick/
Dgen_common.cc330 OpKind op = kOpInvalid; in GenIntNarrowing() local
333 op = kOp2Byte; in GenIntNarrowing()
336 op = kOp2Short; in GenIntNarrowing()
339 op = kOp2Char; in GenIntNarrowing()
344 OpRegReg(op, rl_result.reg, rl_src.reg); in GenIntNarrowing()
1424 OpKind op = kOpBkpt; in GenArithOpInt() local
1432 op = kOpNeg; in GenArithOpInt()
1436 op = kOpMvn; in GenArithOpInt()
1441 op = kOpAdd; in GenArithOpInt()
1445 op = kOpSub; in GenArithOpInt()
[all …]
/art/test/701-easy-div-rem/
DgenMain.py57 for op, op_name in (('/', 'Div'), ('%', 'Rem')):
58 local_vars['@OP@'] = op
/art/test/000-nop/
Dinfo.txt1 This is a sample no-op test, which does at least serve to verify that the
/art/compiler/dex/portable/
Dmir_to_gbc.h123 ::llvm::Value* GenArithOp(OpKind op, bool is_long, ::llvm::Value* src1,
125 void ConvertFPArithOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1,
131 void ConvertArithOp(OpKind op, RegLocation rl_dest, RegLocation rl_src1,
133 void ConvertArithOpLit(OpKind op, RegLocation rl_dest, RegLocation rl_src1,
/art/runtime/base/
Dmutex-inl.h42 static inline int futex(volatile int *uaddr, int op, int val, const struct timespec *timeout, volat… in futex() argument
43 return syscall(SYS_futex, uaddr, op, val, timeout, uaddr2, val3); in futex()

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