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Searched refs:BUILD_VECTOR (Results 1 – 25 of 38) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Darm64-build-vector.ll48 ; fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
49 ; -> (BUILD_VECTOR A, B, ..., C, D, ...)
Darm64-ext.ll95 ; chosen to reach lowering phase as a BUILD_VECTOR.
Daarch64-smull.ll235 ; Do not use SMULL if the BUILD_VECTOR element values are too big.
269 ; Do not use SMULL if the BUILD_VECTOR element values are too big.
Darm64-dup.ll295 ; We used to spot this as a BUILD_VECTOR implementable by dup, but assume that
298 ; BUILD_VECTOR will have an i32 as its source). In that case, the operation is
/external/llvm/lib/Target/R600/
DR600ISelLowering.cpp699 return DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2f32, in LowerOperation()
1353 SDValue Input = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, Src); in LowerSTORE()
1531 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, NewVT, in LowerLOAD()
1613 LoweredLoad = DAG.getNode(ISD::BUILD_VECTOR, DL, TargetVT, Loads); in LowerLOAD()
1727 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); in CompactSwizzlableVector()
1763 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry), in CompactSwizzlableVector()
1769 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); in ReorganizeVector()
1801 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry), in ReorganizeVector()
1808 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR); in OptimizeSwizzle()
1895 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
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DSIISelLowering.cpp183 case ISD::BUILD_VECTOR: in SITargetLowering()
576 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, Regs)); in LowerFormalArguments()
1037 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i32, Lo, Hi); in LowerSELECT()
1343 return DAG.getNode(ISD::BUILD_VECTOR, DL, FloatVT, Ops); in performUCharToFloatCombine()
DAMDGPUISelLowering.cpp848 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args); in LowerCONCAT_VECTORS()
860 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args); in LowerEXTRACT_SUBVECTOR()
1219 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads), in ScalarizeVectorLoad()
1969 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, in LowerFTRUNC()
2223 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi); in LowerFP64_TO_INT()
2269 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args); in LowerSIGN_EXTEND_INREG()
/external/llvm/test/CodeGen/X86/
Dvbinop-simplify-bug.ll12 ; Cannot select: 0x2e329d0: v4i32 = BUILD_VECTOR 0x2e2ea00, 0x2e2ea00, 0x2e2ea00, 0x2e2ea00
D2011-12-28-vselecti8.ll7 ; wider BUILD_VECTOR. This causes the introduction of a new
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
487 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op); in ScalarizeVecOp_UnaryOp()
496 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops); in ScalarizeVecOp_CONCAT_VECTORS()
588 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; in SplitVectorResult()
775 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps); in SplitVecRes_BUILD_VECTOR()
778 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps); in SplitVecRes_BUILD_VECTOR()
1245 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps); in SplitVecRes_VECTOR_SHUFFLE()
1594 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts); in SplitVecOp_CONCAT_VECTORS()
1724 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; in WidenVectorResult()
2060 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, Ops); in WidenVecRes_Convert()
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DLegalizeVectorOps.cpp615 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, in ExpandLoad()
727 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand) in ExpandSELECT()
742 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops); in ExpandSELECT()
841 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, DL, SrcVT, BuildVectorOperands); in ExpandZERO_EXTEND_VECTOR_INREG()
999 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in UnrollVSETCC()
DLegalizeTypesGeneric.cpp364 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, in ExpandOp_BITCAST()
398 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, in ExpandOp_BUILD_VECTOR()
460 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in ExpandOp_SCALAR_TO_VECTOR()
DSelectionDAG.cpp102 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllOnes()
150 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllZeros()
186 if (N->getOpcode() != ISD::BUILD_VECTOR) in isBuildVectorOfConstantSDNodes()
202 if (N->getOpcode() != ISD::BUILD_VECTOR) in isBuildVectorOfConstantFPSDNodes()
222 if (N->getOpcode() != ISD::BUILD_VECTOR) in isScalarToVector()
750 case ISD::BUILD_VECTOR: { in VerifySDNode()
1165 getNode(ISD::BUILD_VECTOR, SDLoc(), ViaVecVT, in getConstant()
1193 Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Ops); in getConstant()
1236 Result = getNode(ISD::BUILD_VECTOR, SDLoc(), VT, Ops); in getConstantFP()
1600 SDValue NewBV = getNode(ISD::BUILD_VECTOR, dl, BuildVT, Ops); in getVectorShuffle()
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DDAGCombiner.cpp1376 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); in visit()
1815 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in tryFoldToZero()
4952 Cond.getOpcode() == ISD::BUILD_VECTOR); in ConvertSelectToConcatVector()
5347 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode(); in tryToFoldExtendOfConstant()
6006 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, in visitZERO_EXTEND()
6024 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, OneOps)); in visitZERO_EXTEND()
6554 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Elts); in visitSIGN_EXTEND_INREG()
6647 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && in visitTRUNCATE()
6668 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds); in visitTRUNCATE()
6804 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && in visitBITCAST()
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DLegalizeIntegerTypes.cpp89 case ISD::BUILD_VECTOR: in PromoteIntegerResult()
840 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break; in PromoteIntegerOperand()
2518 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break; in ExpandIntegerOperand()
2952 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
2995 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops); in PromoteIntRes_BUILD_VECTOR()
3043 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops); in PromoteIntRes_CONCAT_VECTORS()
3099 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps); in PromoteIntOp_CONCAT_VECTORS()
DSelectionDAGDumper.cpp121 case ISD::BUILD_VECTOR: return "BUILD_VECTOR"; in getOperationName()
/external/llvm/test/CodeGen/ARM/
Dvector-DAGCombine.ll72 ; Test folding a binary vector operation with constant BUILD_VECTOR
136 ; a BUILD_VECTOR with i32 0 operands, which did not match the i16 operands
137 ; of the other BUILD_VECTOR.
Dvext.ll111 ; chosen to reach lowering phase as a BUILD_VECTOR.
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h257 BUILD_VECTOR, enumerator
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp788 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in X86TargetLowering()
857 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in X86TargetLowering()
879 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); in X86TargetLowering()
880 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); in X86TargetLowering()
1207 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in X86TargetLowering()
1347 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom); in X86TargetLowering()
1348 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom); in X86TargetLowering()
1400 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in X86TargetLowering()
1452 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in X86TargetLowering()
1558 setTargetDAGCombine(ISD::BUILD_VECTOR); in X86TargetLowering()
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp165 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in InitAMDILLowering()
220 setOperationAction(ISD::BUILD_VECTOR, MVT::Other, Custom); in InitAMDILLowering()
DAMDGPUISelLowering.cpp91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); in LowerOperation()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp258 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); in addMSAIntType()
307 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); in addMSAFloatType()
377 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); in LowerOperation()
1392 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, in lowerMSASplatZExt()
1432 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, in getBuildVectorSplat()
1462 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp, in lowerMSABinaryBitImmIntr()
1845 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, Ops); in lowerINTRINSIC_WO_CHAIN()
2670 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, Ops); in lowerVECTOR_SHUFFLE_VSHF()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp119 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in addTypeForNEON()
564 setTargetDAGCombine(ISD::BUILD_VECTOR); in ARMTargetLowering()
1109 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; in getTargetNodeName()
5118 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerBUILD_VECTOR()
5154 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerBUILD_VECTOR()
5461 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask)); in LowerVECTOR_SHUFFLEv8i8()
5464 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask)); in LowerVECTOR_SHUFFLEv8i8()
5513 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR && in LowerVECTOR_SHUFFLE()
5617 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops); in LowerVECTOR_SHUFFLE()
5688 BVN->getOpcode() != ISD::BUILD_VECTOR) in isExtendedBUILD_VECTOR()
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DARMISelLowering.h173 BUILD_VECTOR, enumerator

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