Home
last modified time | relevance | path

Searched refs:FP_TO_SINT (Results 1 – 25 of 34) sorted by relevance

12

/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp129 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
131 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 3 }, in getCastInstrCost()
133 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
147 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
149 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 }, in getCastInstrCost()
151 { ISD::FP_TO_SINT, MVT::v16i16, MVT::v16f32, 8 }, in getCastInstrCost()
165 { ISD::FP_TO_SINT, MVT::i1, MVT::f32, 2 }, in getCastInstrCost()
167 { ISD::FP_TO_SINT, MVT::i1, MVT::f64, 2 }, in getCastInstrCost()
169 { ISD::FP_TO_SINT, MVT::i8, MVT::f32, 2 }, in getCastInstrCost()
171 { ISD::FP_TO_SINT, MVT::i8, MVT::f64, 2 }, in getCastInstrCost()
[all …]
DARMISelLowering.cpp111 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
116 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
535 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
568 setTargetDAGCombine(ISD::FP_TO_SINT); in ARMTargetLowering()
620 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
622 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
3803 if (Op.getOpcode() == ISD::FP_TO_SINT) in LowerFP_TO_INT()
5978 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
6015 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
6124 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp223 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, in getCastInstrCost()
224 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }, in getCastInstrCost()
225 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f64, 1 }, in getCastInstrCost()
231 { ISD::FP_TO_SINT, MVT::v2i64, MVT::v2f32, 2 }, in getCastInstrCost()
232 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, in getCastInstrCost()
233 { ISD::FP_TO_SINT, MVT::v2i8, MVT::v2f32, 1 }, in getCastInstrCost()
239 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
240 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 2 }, in getCastInstrCost()
245 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, in getCastInstrCost()
246 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, in getCastInstrCost()
[all …]
DAArch64ISelLowering.cpp186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in AArch64TargetLowering()
187 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AArch64TargetLowering()
188 setOperationAction(ISD::FP_TO_SINT, MVT::i128, Custom); in AArch64TargetLowering()
546 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); in AArch64TargetLowering()
678 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom); in addTypeForNEON()
1610 if (Op.getOpcode() == ISD::FP_TO_SINT) in LowerFP_TO_INT()
2012 case ISD::FP_TO_SINT: in LowerOperation()
8899 case ISD::FP_TO_SINT: in ReplaceNodeResults()
/external/llvm/test/CodeGen/X86/
Davx-fp2int.ll3 ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
Dhalf.ll117 ; FP_TO_UINT is expanded using FP_TO_SINT
/external/llvm/test/CodeGen/R600/
Dfcmp.ll19 ; SET* + FP_TO_SINT
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp294 case ISD::FP_TO_SINT: in LegalizeOp()
375 case ISD::FP_TO_SINT: in Promote()
377 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT); in Promote()
461 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) { in PromoteFP_TO_INT()
462 NewOpc = ISD::FP_TO_SINT; in PromoteFP_TO_INT()
DLegalizeFloatTypes.cpp687 case ISD::FP_TO_SINT: Res = SoftenFloatOp_FP_TO_SINT(N); break; in SoftenFloatOperand()
1376 case ISD::FP_TO_SINT: Res = ExpandFloatOp_FP_TO_SINT(N); break; in ExpandFloatOperand()
1483 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); in ExpandFloatOp_FP_TO_SINT()
1507 DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, in ExpandFloatOp_FP_TO_UINT()
1513 DAG.getNode(ISD::FP_TO_SINT, dl, in ExpandFloatOp_FP_TO_UINT()
1612 case ISD::FP_TO_SINT: in PromoteFloatOperand()
DLegalizeVectorTypes.cpp88 case ISD::FP_TO_SINT: in ScalarizeVectorResult()
430 case ISD::FP_TO_SINT: in ScalarizeVectorOperand()
630 case ISD::FP_TO_SINT: in SplitVectorResult()
1310 case ISD::FP_TO_SINT: in SplitVectorOperand()
1785 case ISD::FP_TO_SINT: in WidenVectorResult()
2638 case ISD::FP_TO_SINT: in WidenVectorOperand()
DSelectionDAGDumper.cpp240 case ISD::FP_TO_SINT: return "fp_to_sint"; in getOperationName()
DLegalizeDAG.cpp2667 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { in PromoteLegalFP_TO_INT()
2668 OpToUse = ISD::FP_TO_SINT; in PromoteLegalFP_TO_INT()
3042 case ISD::FP_TO_SINT: in ExpandNode()
3058 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); in ExpandNode()
3059 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, in ExpandNode()
4078 case ISD::FP_TO_SINT: in PromoteNode()
4080 Node->getOpcode() == ISD::FP_TO_SINT, dl); in PromoteNode()
DLegalizeIntegerTypes.cpp100 case ISD::FP_TO_SINT: in PromoteIntegerResult()
402 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
403 NewOpc = ISD::FP_TO_SINT; in PromoteIntRes_FP_TO_XINT()
1250 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break; in ExpandIntegerResult()
/external/llvm/lib/Target/X86/
DREADME-FPStack.txt50 FP_TO_SINT when the source operand is already in memory.
DX86TargetTransformInfo.cpp633 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 7 }, in getCastInstrCost()
634 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 }, in getCastInstrCost()
DX86ISelLowering.cpp217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); in X86TargetLowering()
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); in X86TargetLowering()
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); in X86TargetLowering()
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); in X86TargetLowering()
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); in X86TargetLowering()
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); in X86TargetLowering()
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); in X86TargetLowering()
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in X86TargetLowering()
919 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in X86TargetLowering()
1062 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote); in X86TargetLowering()
[all …]
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h427 FP_TO_SINT, enumerator
/external/mesa3d/src/gallium/drivers/radeon/
DR600ISelLowering.cpp417 ConversionOp = ISD::FP_TO_SINT; in LowerSELECT_CC()
492 Cond = DAG.getNode(ISD::FP_TO_SINT, DL, MVT::i32, in LowerSELECT_CC()
DAMDILISelLowering.cpp545 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq); in LowerSDIV24()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1452 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote); in HexagonTargetLowering()
1457 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); in HexagonTargetLowering()
1462 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); in HexagonTargetLowering()
1467 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in HexagonTargetLowering()
1472 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal); in HexagonTargetLowering()
1484 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); in HexagonTargetLowering()
1542 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand); in HexagonTargetLowering()
1545 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand); in HexagonTargetLowering()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in PPCTargetLowering()
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in PPCTargetLowering()
497 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in PPCTargetLowering()
610 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal); in PPCTargetLowering()
654 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal); in PPCTargetLowering()
704 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal); in PPCTargetLowering()
5870 Op.getOpcode() == ISD::FP_TO_SINT in LowerFP_TO_INTForReuse()
5876 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) && in LowerFP_TO_INTForReuse()
[all …]
/external/llvm/lib/Target/R600/
DR600ISelLowering.cpp86 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in R600TargetLowering()
161 setTargetDAGCombine(ISD::FP_TO_SINT); in R600TargetLowering()
867 case ISD::FP_TO_SINT: { in ReplaceNodeResults()
1856 case ISD::FP_TO_SINT: { in PerformDAGCombine()
DAMDGPUISelLowering.cpp300 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in AMDGPUTargetLowering()
318 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in AMDGPUTargetLowering()
620 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); in LowerOperation()
1551 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT; in LowerDIVREM24()
2219 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL, in LowerFP64_TO_INT()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp1421 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in SparcTargetLowering()
1423 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in SparcTargetLowering()
2796 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, in LowerOperation()
3189 case ISD::FP_TO_SINT: in ReplaceNodeResults()
3195 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp266 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in MipsTargetLowering()
277 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); in MipsTargetLowering()
859 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG); in LowerOperation()
2250 if (Val.getOpcode() != ISD::FP_TO_SINT) in lowerFP_TO_SINT_STORE()

12