Searched refs:Arm64Mir2Lir (Results 1 – 7 of 7) sorted by relevance
/art/compiler/dex/quick/arm64/ |
D | target_arm64.cc | 87 RegLocation Arm64Mir2Lir::LocCReturn() { in LocCReturn() 91 RegLocation Arm64Mir2Lir::LocCReturnRef() { in LocCReturnRef() 95 RegLocation Arm64Mir2Lir::LocCReturnWide() { in LocCReturnWide() 99 RegLocation Arm64Mir2Lir::LocCReturnFloat() { in LocCReturnFloat() 103 RegLocation Arm64Mir2Lir::LocCReturnDouble() { in LocCReturnDouble() 108 RegStorage Arm64Mir2Lir::TargetReg(SpecialTargetRegister reg) { in TargetReg() 146 ResourceMask Arm64Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { in GetRegMaskCommon() 160 ResourceMask Arm64Mir2Lir::GetPCUseDefEncoding() const { in GetPCUseDefEncoding() 168 void Arm64Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, in SetupTargetResourceMasks() 190 ArmConditionCode Arm64Mir2Lir::ArmConditionEncoding(ConditionCode ccode) { in ArmConditionEncoding() [all …]
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D | utility_arm64.cc | 28 int32_t Arm64Mir2Lir::EncodeImmSingle(uint32_t bits) { in EncodeImmSingle() 60 int32_t Arm64Mir2Lir::EncodeImmDouble(uint64_t bits) { in EncodeImmDouble() 92 size_t Arm64Mir2Lir::GetLoadStoreSize(LIR* lir) { in GetLoadStoreSize() 101 size_t Arm64Mir2Lir::GetInstructionOffset(LIR* lir) { in GetInstructionOffset() 112 LIR* Arm64Mir2Lir::LoadFPConstantValue(RegStorage r_dest, int32_t value) { in LoadFPConstantValue() 136 LIR* Arm64Mir2Lir::LoadFPConstantValueWide(RegStorage r_dest, int64_t value) { in LoadFPConstantValueWide() 184 int Arm64Mir2Lir::EncodeLogicalImmediate(bool is_wide, uint64_t value) { in EncodeLogicalImmediate() 311 bool Arm64Mir2Lir::InexpensiveConstantInt(int32_t value ATTRIBUTE_UNUSED) { in InexpensiveConstantInt() 317 bool Arm64Mir2Lir::InexpensiveConstantFloat(int32_t value) { in InexpensiveConstantFloat() 321 bool Arm64Mir2Lir::InexpensiveConstantLong(int64_t value) { in InexpensiveConstantLong() [all …]
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D | fp_arm64.cc | 26 void Arm64Mir2Lir::GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, in GenArithOpFloat() 68 void Arm64Mir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble() 121 void Arm64Mir2Lir::GenMultiplyByConstantFloat(RegLocation rl_dest, RegLocation rl_src1, in GenMultiplyByConstantFloat() 132 void Arm64Mir2Lir::GenMultiplyByConstantDouble(RegLocation rl_dest, RegLocation rl_src1, in GenMultiplyByConstantDouble() 147 void Arm64Mir2Lir::GenConversion(Instruction::Code opcode, in GenConversion() 229 void Arm64Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, in GenFusedFPCmpBranch() 279 void Arm64Mir2Lir::GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, in GenCmpFP() 337 void Arm64Mir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) { in GenNegFloat() 345 void Arm64Mir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) { in GenNegDouble() 372 bool Arm64Mir2Lir::GenInlinedAbsFloat(CallInfo* info) { in GenInlinedAbsFloat() [all …]
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D | call_arm64.cc | 55 void Arm64Mir2Lir::GenLargeSparseSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { in GenLargeSparseSwitch() 104 void Arm64Mir2Lir::GenLargePackedSwitch(MIR* mir, uint32_t table_offset, RegLocation rl_src) { in GenLargePackedSwitch() 155 void Arm64Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { in GenMonitorEnter() 209 void Arm64Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { in GenMonitorExit() 266 void Arm64Mir2Lir::GenMoveException(RegLocation rl_dest) { in GenMoveException() 274 void Arm64Mir2Lir::UnconditionallyMarkGCCard(RegStorage tgt_addr_reg) { in UnconditionallyMarkGCCard() 290 void Arm64Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { in GenEntrySequence() 405 void Arm64Mir2Lir::GenExitSequence() { in GenExitSequence() 422 void Arm64Mir2Lir::GenSpecialExitSequence() { in GenSpecialExitSequence() 426 void Arm64Mir2Lir::GenSpecialEntryForSuspend() { in GenSpecialEntryForSuspend() [all …]
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D | int_arm64.cc | 35 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch() 40 LIR* Arm64Mir2Lir::OpIT(ConditionCode ccode, const char* guide) { in OpIT() 46 void Arm64Mir2Lir::OpEndIT(LIR* it) { in OpEndIT() 57 void Arm64Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, in GenCmpLong() 71 void Arm64Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, in GenShiftOpLong() 99 void Arm64Mir2Lir::GenSelect(int32_t true_val, int32_t false_val, ConditionCode ccode, in GenSelect() 183 void Arm64Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32() 191 void Arm64Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { in GenSelect() 223 void Arm64Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { in GenFusedLongCmpBranch() 268 LIR* Arm64Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, in OpCmpImmBranch() [all …]
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D | assemble_arm64.cc | 111 const A64EncodingMap Arm64Mir2Lir::EncodingMap[kA64Last] = { 664 void Arm64Mir2Lir::ReplaceFixup(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { in ReplaceFixup() 675 void Arm64Mir2Lir::InsertFixupBefore(LIR* prev_lir, LIR* orig_lir, LIR* new_lir) { in InsertFixupBefore() 688 uint8_t* Arm64Mir2Lir::EncodeLIRs(uint8_t* write_pos, LIR* lir) { in EncodeLIRs() 871 void Arm64Mir2Lir::AssembleLIR() { in AssembleLIR() 1101 size_t Arm64Mir2Lir::GetInsnSize(LIR* lir) { in GetInsnSize() 1108 uint32_t Arm64Mir2Lir::LinkFixupInsns(LIR* head_lir, LIR* tail_lir, uint32_t offset) { in LinkFixupInsns() 1141 void Arm64Mir2Lir::AssignDataOffsets() { in AssignDataOffsets()
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D | codegen_arm64.h | 28 class Arm64Mir2Lir FINAL : public Mir2Lir { 51 Arm64Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
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