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Searched refs:MVT (Results 1 – 25 of 205) sorted by relevance

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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp93 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty); in getArithmeticInstrCost()
119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle. in getArithmeticInstrCost()
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
135 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
136 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
137 { ISD::SRA, MVT::v16i32, 1 }, in getArithmeticInstrCost()
138 { ISD::SHL, MVT::v8i64, 1 }, in getArithmeticInstrCost()
[all …]
DX86ISelLowering.cpp76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize()); in X86TargetLowering()
133 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
134 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
135 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
137 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
139 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering()
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand); in X86TargetLowering()
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand); in X86TargetLowering()
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); in X86TargetLowering()
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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp57 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
58 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
59 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
64 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src); in getCastInstrCost()
79 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
80 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
81 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
82 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, in getCastInstrCost()
83 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
84 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
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DARMISelDAGToDAG.cpp88 return CurDAG->getTargetConstant(Imm, dl, MVT::i32); in getI32Imm()
138 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(N), MVT::i32); in SelectCMOVPred()
139 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32); in SelectCMOVPred()
296 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { in isInt32Immediate()
409 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32, in PreprocessISelDAG()
412 MVT::i32)); in PreprocessISelDAG()
413 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32, in PreprocessISelDAG()
415 CurDAG->getConstant(And_imm, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
416 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32, in PreprocessISelDAG()
417 N1, CurDAG->getConstant(TZ, SDLoc(Srl), MVT::i32)); in PreprocessISelDAG()
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/external/llvm/include/llvm/CodeGen/
DMachineValueType.h29 class MVT {
181 LLVM_CONSTEXPR MVT() : SimpleTy(INVALID_SIMPLE_VALUE_TYPE) {} in MVT() function
182 LLVM_CONSTEXPR MVT(SimpleValueType SVT) : SimpleTy(SVT) { } in MVT() function
184 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
185 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
186 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
187 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy; }
188 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
189 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
193 return (SimpleTy >= MVT::FIRST_VALUETYPE && in isValid()
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/external/llvm/lib/IR/
DValueTypes.cpp124 case MVT::i1: return "i1"; in getEVTString()
125 case MVT::i8: return "i8"; in getEVTString()
126 case MVT::i16: return "i16"; in getEVTString()
127 case MVT::i32: return "i32"; in getEVTString()
128 case MVT::i64: return "i64"; in getEVTString()
129 case MVT::i128: return "i128"; in getEVTString()
130 case MVT::f16: return "f16"; in getEVTString()
131 case MVT::f32: return "f32"; in getEVTString()
132 case MVT::f64: return "f64"; in getEVTString()
133 case MVT::f80: return "f80"; in getEVTString()
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/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp191 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 }, in getCastInstrCost()
193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 }, in getCastInstrCost()
194 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 }, in getCastInstrCost()
197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
198 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
199 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
200 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 2 }, in getCastInstrCost()
201 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
202 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i8, 3 }, in getCastInstrCost()
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DAArch64ISelDAGToDAG.cpp272 Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32); in SelectArithImmed()
273 Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32); in SelectArithImmed()
298 if (N.getValueType() == MVT::i32) in SelectNegArithImmed()
306 return SelectArithImmed(CurDAG->getConstant(Immed, SDLoc(N), MVT::i32), Val, in SelectNegArithImmed()
355 Shift = CurDAG->getTargetConstant(ShVal, SDLoc(N), MVT::i32); in SelectShiftedRegister()
374 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
376 else if (!IsLoadStore && SrcVT == MVT::i16) in getExtendTypeForNode()
378 else if (SrcVT == MVT::i32) in getExtendTypeForNode()
380 assert(SrcVT != MVT::i64 && "extend from 64-bits?"); in getExtendTypeForNode()
386 if (!IsLoadStore && SrcVT == MVT::i8) in getExtendTypeForNode()
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DAArch64ISelLowering.cpp63 static const MVT MVT_CC = MVT::i32;
77 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass); in AArch64TargetLowering()
78 addRegisterClass(MVT::i64, &AArch64::GPR64allRegClass); in AArch64TargetLowering()
81 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
82 addRegisterClass(MVT::f32, &AArch64::FPR32RegClass); in AArch64TargetLowering()
83 addRegisterClass(MVT::f64, &AArch64::FPR64RegClass); in AArch64TargetLowering()
84 addRegisterClass(MVT::f128, &AArch64::FPR128RegClass); in AArch64TargetLowering()
88 addRegisterClass(MVT::v16i8, &AArch64::FPR8RegClass); in AArch64TargetLowering()
89 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass); in AArch64TargetLowering()
91 addDRTypeForNEON(MVT::v2f32); in AArch64TargetLowering()
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DAArch64FastISel.cpp140 bool isTypeLegal(Type *Ty, MVT &VT);
141 bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
145 bool simplifyAddress(Address &Addr, MVT VT);
154 bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
159 unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
162 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
165 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
168 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
173 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
182 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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/external/llvm/utils/TableGen/
DCodeGenTarget.cpp38 MVT::SimpleValueType llvm::getValueType(Record *Rec) { in getValueType()
39 return (MVT::SimpleValueType)Rec->getValueAsInt("Value"); in getValueType()
42 std::string llvm::getName(MVT::SimpleValueType T) { in getName()
44 case MVT::Other: return "UNKNOWN"; in getName()
45 case MVT::iPTR: return "TLI.getPointerTy()"; in getName()
46 case MVT::iPTRAny: return "TLI.getPointerTy()"; in getName()
51 std::string llvm::getEnumName(MVT::SimpleValueType T) { in getEnumName()
53 case MVT::Other: return "MVT::Other"; in getEnumName()
54 case MVT::i1: return "MVT::i1"; in getEnumName()
55 case MVT::i8: return "MVT::i8"; in getEnumName()
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp102 static bool IsHvxVectorType(MVT ty);
105 CC_Hexagon(unsigned ValNo, MVT ValVT,
106 MVT LocVT, CCValAssign::LocInfo LocInfo,
110 CC_Hexagon32(unsigned ValNo, MVT ValVT,
111 MVT LocVT, CCValAssign::LocInfo LocInfo,
115 CC_Hexagon64(unsigned ValNo, MVT ValVT,
116 MVT LocVT, CCValAssign::LocInfo LocInfo,
120 CC_HexagonVector(unsigned ValNo, MVT ValVT,
121 MVT LocVT, CCValAssign::LocInfo LocInfo,
125 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
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DHexagonISelDAGToDAG.cpp121 return CurDAG->getTargetConstant(bitPos, DL, MVT::i32); in XformMskToBitPosU5Imm()
147 return CurDAG->getTargetConstant(-Imm, DL, MVT::i32); in XformM5ToU5Imm()
154 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i8); in XformU7ToU7M1Imm()
159 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32); in XformSToSM1Imm()
165 return CurDAG->getTargetConstant(Imm - 1, DL, MVT::i32); in XformUToUM1Imm()
170 return CurDAG->getTargetConstant(Imm - 2, DL, MVT::i32); in XformSToSM2Imm()
175 return CurDAG->getTargetConstant(Imm - 3, DL, MVT::i32); in XformSToSM3Imm()
265 SDValue TargetConst = CurDAG->getTargetConstant(Val, dl, MVT::i32); in SelectIndexedLoadSignExtend64()
266 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32, in SelectIndexedLoadSignExtend64()
267 MVT::Other, Base, TargetConst, in SelectIndexedLoadSignExtend64()
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp51 (int)MVT::i8, in InitAMDILLowering()
52 (int)MVT::i16, in InitAMDILLowering()
53 (int)MVT::i32, in InitAMDILLowering()
54 (int)MVT::f32, in InitAMDILLowering()
55 (int)MVT::f64, in InitAMDILLowering()
56 (int)MVT::i64, in InitAMDILLowering()
57 (int)MVT::v2i8, in InitAMDILLowering()
58 (int)MVT::v4i8, in InitAMDILLowering()
59 (int)MVT::v2i16, in InitAMDILLowering()
60 (int)MVT::v4i16, in InitAMDILLowering()
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/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp441 if (OpVT == MVT::f16) { in getFPEXT()
442 if (RetVT == MVT::f32) in getFPEXT()
444 } else if (OpVT == MVT::f32) { in getFPEXT()
445 if (RetVT == MVT::f64) in getFPEXT()
447 if (RetVT == MVT::f128) in getFPEXT()
449 } else if (OpVT == MVT::f64) { in getFPEXT()
450 if (RetVT == MVT::f128) in getFPEXT()
460 if (RetVT == MVT::f16) { in getFPROUND()
461 if (OpVT == MVT::f32) in getFPROUND()
463 if (OpVT == MVT::f64) in getFPROUND()
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/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.h27 class MVT; variable
39 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
41 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
43 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
45 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
47 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
49 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
51 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
53 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
55 void DecodePSHUFLWMask(MVT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
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/external/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp42 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); in SITargetLowering()
43 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); in SITargetLowering()
45 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); in SITargetLowering()
46 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); in SITargetLowering()
48 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass); in SITargetLowering()
49 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass); in SITargetLowering()
51 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass); in SITargetLowering()
52 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); in SITargetLowering()
53 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass); in SITargetLowering()
55 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass); in SITargetLowering()
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DAMDGPUISelLowering.cpp34 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT, in allocateStack()
53 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentMemType()
62 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); in getEquivalentLoadRegType()
68 setOperationAction(ISD::Constant, MVT::i32, Legal); in AMDGPUTargetLowering()
69 setOperationAction(ISD::Constant, MVT::i64, Legal); in AMDGPUTargetLowering()
70 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in AMDGPUTargetLowering()
71 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in AMDGPUTargetLowering()
73 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in AMDGPUTargetLowering()
74 setOperationAction(ISD::BRIND, MVT::Other, Expand); in AMDGPUTargetLowering()
77 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); in AMDGPUTargetLowering()
[all …]
DR600ISelLowering.cpp36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
37 addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
38 addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass); in R600TargetLowering()
39 addRegisterClass(MVT::i32, &AMDGPU::R600_Reg32RegClass); in R600TargetLowering()
40 addRegisterClass(MVT::v2f32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass); in R600TargetLowering()
46 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
47 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in R600TargetLowering()
48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
49 setCondCodeAction(ISD::SETLE, MVT::f32, Expand); in R600TargetLowering()
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/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
145 bool isTypeLegal(Type *Ty, MVT &VT);
146 bool isLoadTypeLegal(Type *Ty, MVT &VT);
156 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
159 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
161 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
163 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
165 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
166 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
167 unsigned PPCMaterializeInt(const ConstantInt *CI, MVT VT,
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DPPCISelLowering.cpp70 addRegisterClass(MVT::i32, &PPC::GPRCRegClass); in PPCTargetLowering()
72 addRegisterClass(MVT::f32, &PPC::F4RCRegClass); in PPCTargetLowering()
73 addRegisterClass(MVT::f64, &PPC::F8RCRegClass); in PPCTargetLowering()
77 for (MVT VT : MVT::integer_valuetypes()) { in PPCTargetLowering()
78 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in PPCTargetLowering()
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in PPCTargetLowering()
82 setTruncStoreAction(MVT::f64, MVT::f32, Expand); in PPCTargetLowering()
85 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp596 return CurDAG->getMachineNode(NVPTX::texsurf_handles, SDLoc(N), MVT::i64, in SelectTexSurfHandle()
689 MVT SimpleVT = LoadedVT.getSimpleVT(); in SelectLoad()
707 MVT ScalarVT = SimpleVT.getScalarType(); in SelectLoad()
724 MVT::SimpleValueType TargetVT = LD->getSimpleValueType(0).SimpleTy; in SelectLoad()
728 case MVT::i8: in SelectLoad()
731 case MVT::i16: in SelectLoad()
734 case MVT::i32: in SelectLoad()
737 case MVT::i64: in SelectLoad()
740 case MVT::f32: in SelectLoad()
743 case MVT::f64: in SelectLoad()
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/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_SRet()
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_SRet()
52 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Split_64()
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Split_64()
80 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT, in CC_Sparc_Assign_Ret_Split_64()
81 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc_Assign_Ret_Split_64()
104 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, in CC_Sparc64_Full()
105 MVT &LocVT, CCValAssign::LocInfo &LocInfo, in CC_Sparc64_Full()
107 assert((LocVT == MVT::f32 || LocVT == MVT::f128 in CC_Sparc64_Full()
112 unsigned size = (LocVT == MVT::f128) ? 16 : 8; in CC_Sparc64_Full()
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/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp111 bool isTypeLegal(Type *Ty, MVT &VT);
112 bool isTypeSupported(Type *Ty, MVT &VT);
113 bool isLoadTypeLegal(Type *Ty, MVT &VT);
120 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
122 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
124 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
126 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
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/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp77 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); in XCoreTargetLowering()
91 setOperationAction(ISD::BR_CC, MVT::i32, Expand); in XCoreTargetLowering()
92 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand); in XCoreTargetLowering()
93 setOperationAction(ISD::ADDC, MVT::i32, Expand); in XCoreTargetLowering()
94 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
95 setOperationAction(ISD::SUBC, MVT::i32, Expand); in XCoreTargetLowering()
96 setOperationAction(ISD::SUBE, MVT::i32, Expand); in XCoreTargetLowering()
99 setOperationAction(ISD::ADD, MVT::i64, Custom); in XCoreTargetLowering()
100 setOperationAction(ISD::SUB, MVT::i64, Custom); in XCoreTargetLowering()
101 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); in XCoreTargetLowering()
[all …]

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