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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp54 SDValue LegalizeOp(SDValue Op);
57 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
60 SDValue UnrollVSETCC(SDValue Op);
66 SDValue Expand(SDValue Op);
73 SDValue ExpandUINT_TO_FLOAT(SDValue Op);
76 SDValue ExpandSEXTINREG(SDValue Op);
83 SDValue ExpandANY_EXTEND_VECTOR_INREG(SDValue Op);
90 SDValue ExpandSIGN_EXTEND_VECTOR_INREG(SDValue Op);
96 SDValue ExpandZERO_EXTEND_VECTOR_INREG(SDValue Op);
99 SDValue ExpandBSWAP(SDValue Op);
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/external/llvm/include/llvm/CodeGen/
DMachineOperand.h580 MachineOperand Op(MachineOperand::MO_Immediate); in CreateImm()
581 Op.setImm(Val); in CreateImm()
582 return Op; in CreateImm()
586 MachineOperand Op(MachineOperand::MO_CImmediate); in CreateCImm()
587 Op.Contents.CI = CI; in CreateCImm()
588 return Op; in CreateCImm()
592 MachineOperand Op(MachineOperand::MO_FPImmediate); in CreateFPImm()
593 Op.Contents.CFP = CFP; in CreateFPImm()
594 return Op; in CreateFPImm()
606 MachineOperand Op(MachineOperand::MO_Register);
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DMachineRegisterInfo.h762 MachineOperand *Op; variable
763 explicit defusechain_iterator(MachineOperand *op) : Op(op) { in defusechain_iterator()
776 assert(Op && "Cannot increment end iterator!"); in advance()
777 Op = getNextOperandForReg(Op); in advance()
781 if (Op) { in advance()
782 if (Op->isUse()) in advance()
783 Op = nullptr; in advance()
785 assert(!Op->isDebug() && "Can't have debug defs"); in advance()
789 while (Op && ((!ReturnDefs && Op->isDef()) || in advance()
790 (SkipDebug && Op->isDebug()))) in advance()
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/external/llvm/lib/Target/X86/InstPrinter/
DX86IntelInstPrinter.cpp54 void X86IntelInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, in printSSEAVXCC() argument
56 int64_t Imm = MI->getOperand(Op).getImm(); in printSSEAVXCC()
94 void X86IntelInstPrinter::printXOPCC(const MCInst *MI, unsigned Op, in printXOPCC() argument
96 int64_t Imm = MI->getOperand(Op).getImm(); in printXOPCC()
110 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, in printRoundingControl() argument
112 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; in printRoundingControl()
125 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImm() local
126 if (Op.isImm()) in printPCRelImm()
127 O << formatImm(Op.getImm()); in printPCRelImm()
129 assert(Op.isExpr() && "unknown pcrel immediate operand"); in printPCRelImm()
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DX86ATTInstPrinter.cpp72 void X86ATTInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op, in printSSEAVXCC() argument
74 int64_t Imm = MI->getOperand(Op).getImm(); in printSSEAVXCC()
112 void X86ATTInstPrinter::printXOPCC(const MCInst *MI, unsigned Op, in printXOPCC() argument
114 int64_t Imm = MI->getOperand(Op).getImm(); in printXOPCC()
128 void X86ATTInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op, in printRoundingControl() argument
130 int64_t Imm = MI->getOperand(Op).getImm() & 0x3; in printRoundingControl()
144 const MCOperand &Op = MI->getOperand(OpNo); in printPCRelImm() local
145 if (Op.isImm()) in printPCRelImm()
146 O << formatImm(Op.getImm()); in printPCRelImm()
148 assert(Op.isExpr() && "unknown pcrel immediate operand"); in printPCRelImm()
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/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp360 SDValue MipsSETargetLowering::LowerOperation(SDValue Op, in LowerOperation() argument
362 switch(Op.getOpcode()) { in LowerOperation()
363 case ISD::LOAD: return lowerLOAD(Op, DAG); in LowerOperation()
364 case ISD::STORE: return lowerSTORE(Op, DAG); in LowerOperation()
365 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); in LowerOperation()
366 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); in LowerOperation()
367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); in LowerOperation()
368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
369 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); in LowerOperation()
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); in LowerOperation()
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) in LowerOperation() argument
82 switch (Op.getOpcode()) { in LowerOperation()
84 Op.getNode()->dump(); in LowerOperation()
89 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
90 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
91 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); in LowerOperation()
92 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
93 case ISD::BRCOND: return LowerBRCOND(Op, DAG); in LowerOperation()
95 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
96 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
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DAMDGPUISelLowering.h27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
38 bool isHWTrueValue(SDValue Op) const;
39 bool isHWFalseValue(SDValue Op) const;
56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
67 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
84 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
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DAMDILISelLowering.cpp278 const SDValue Op, in computeMaskedBitsForTargetNode() argument
287 switch (Op.getOpcode()) { in computeMaskedBitsForTargetNode()
291 Op.getOperand(1), in computeMaskedBitsForTargetNode()
297 Op.getOperand(0), in computeMaskedBitsForTargetNode()
317 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const in LowerSDIV() argument
319 EVT OVT = Op.getValueType(); in LowerSDIV()
322 DST = LowerSDIV64(Op, DAG); in LowerSDIV()
324 DST = LowerSDIV32(Op, DAG); in LowerSDIV()
327 DST = LowerSDIV24(Op, DAG); in LowerSDIV()
329 DST = SDValue(Op.getNode(), 0); in LowerSDIV()
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DR600ISelLowering.cpp245 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const in LowerOperation() argument
247 switch (Op.getOpcode()) { in LowerOperation()
248 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
249 case ISD::BR_CC: return LowerBR_CC(Op, DAG); in LowerOperation()
250 case ISD::ROTL: return LowerROTL(Op, DAG); in LowerOperation()
251 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
252 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
254 SDValue Chain = Op.getOperand(0); in LowerOperation()
256 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); in LowerOperation()
261 int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); in LowerOperation()
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/external/opencv3/modules/cudev/include/opencv2/cudev/ptr2d/
Dtransform.hpp61 template <class SrcPtr, class Op> struct UnaryTransformPtr
63 typedef typename Op::result_type value_type;
67 Op op;
69 …__device__ __forceinline__ typename Op::result_type operator ()(typename PtrTraits<SrcPtr>::index_… in operator ()()
75 template <class SrcPtr, class Op> struct UnaryTransformPtrSz : UnaryTransformPtr<SrcPtr, Op>
86 template <class SrcPtr, class Op>
87 __host__ UnaryTransformPtrSz<typename PtrTraits<SrcPtr>::ptr_type, Op>
88 transformPtr(const SrcPtr& src, const Op& op) in transformPtr()
90 UnaryTransformPtrSz<typename PtrTraits<SrcPtr>::ptr_type, Op> ptr; in transformPtr()
98 …tr, class Op> struct PtrTraits< UnaryTransformPtrSz<SrcPtr, Op> > : PtrTraitsBase<UnaryTransformPt…
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/external/llvm/include/llvm/MC/
DMCInst.h112 MCOperand Op; in createReg() local
113 Op.Kind = kRegister; in createReg()
114 Op.RegVal = Reg; in createReg()
115 return Op; in createReg()
118 MCOperand Op; in createImm() local
119 Op.Kind = kImmediate; in createImm()
120 Op.ImmVal = Val; in createImm()
121 return Op; in createImm()
124 MCOperand Op; in createFPImm() local
125 Op.Kind = kFPImmediate; in createFPImm()
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/external/opencv3/modules/cudev/include/opencv2/cudev/functional/
Dtuple_adapter.hpp57 template <class Op, int n> struct UnaryTupleAdapter
59 typedef typename Op::result_type result_type;
61 Op op;
64 __device__ __forceinline__ typename Op::result_type operator ()(const Tuple& t) const in operator ()()
70 template <int n, class Op>
71 __host__ __device__ UnaryTupleAdapter<Op, n> unaryTupleAdapter(const Op& op) in unaryTupleAdapter()
73 UnaryTupleAdapter<Op, n> a; in unaryTupleAdapter()
78 template <class Op, int n0, int n1> struct BinaryTupleAdapter
80 typedef typename Op::result_type result_type;
82 Op op;
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/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
46 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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DAMDGPUISelLowering.cpp601 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, in LowerDYNAMIC_STACKALLOC() argument
610 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, in LowerOperation() argument
612 switch (Op.getOpcode()) { in LowerOperation()
614 Op.getNode()->dump(); in LowerOperation()
618 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG); in LowerOperation()
619 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
620 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
621 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG); in LowerOperation()
622 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); in LowerOperation()
623 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); in LowerOperation()
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/external/clang/lib/CodeGen/
DCGExprComplex.cpp150 ComplexPairTy EmitCast(CastKind CK, Expr *Op, QualType DestTy);
235 ComplexPairTy EmitBinAdd(const BinOpInfo &Op);
236 ComplexPairTy EmitBinSub(const BinOpInfo &Op);
237 ComplexPairTy EmitBinMul(const BinOpInfo &Op);
238 ComplexPairTy EmitBinDiv(const BinOpInfo &Op);
241 const BinOpInfo &Op);
423 ComplexPairTy ComplexExprEmitter::EmitCast(CastKind CK, Expr *Op, in EmitCast() argument
435 return Visit(Op); in EmitCast()
438 LValue origLV = CGF.EmitLValue(Op); in EmitCast()
441 return EmitLoadOfLValue(CGF.MakeAddrLValue(V, DestTy), Op->getExprLoc()); in EmitCast()
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/external/llvm/lib/Target/XCore/
DXCoreISelLowering.h109 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
169 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
172 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
173 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
174 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
175 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
176 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
177 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h231 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
244 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
273 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
455 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
456 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
457 SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
458 SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
461 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
462 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.h389 void LowerAsmOperandForConstraint(SDValue Op,
429 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
456 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
457 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
458 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
470 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
471 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
472 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
473 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
474 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
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DSystemZISelLowering.cpp78 static MachineOperand earlyUseOperand(MachineOperand Op) { in earlyUseOperand() argument
79 if (Op.isReg()) in earlyUseOperand()
80 Op.setIsKill(false); in earlyUseOperand()
81 return Op; in earlyUseOperand()
721 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, in LowerAsmOperandForConstraint() argument
728 if (auto *C = dyn_cast<ConstantSDNode>(Op)) in LowerAsmOperandForConstraint()
730 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op), in LowerAsmOperandForConstraint()
731 Op.getValueType())); in LowerAsmOperandForConstraint()
735 if (auto *C = dyn_cast<ConstantSDNode>(Op)) in LowerAsmOperandForConstraint()
737 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op), in LowerAsmOperandForConstraint()
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/external/llvm/lib/Bitcode/Reader/
DBitstreamReader.cpp55 const BitCodeAbbrevOp &Op) { in readAbbreviatedField() argument
56 assert(!Op.isLiteral() && "Not to be used with literals!"); in readAbbreviatedField()
59 switch (Op.getEncoding()) { in readAbbreviatedField()
64 assert((unsigned)Op.getEncodingData() <= Cursor.MaxChunkSize); in readAbbreviatedField()
65 return Cursor.Read((unsigned)Op.getEncodingData()); in readAbbreviatedField()
67 assert((unsigned)Op.getEncodingData() <= Cursor.MaxChunkSize); in readAbbreviatedField()
68 return Cursor.ReadVBR64((unsigned)Op.getEncodingData()); in readAbbreviatedField()
76 const BitCodeAbbrevOp &Op) { in skipAbbreviatedField() argument
77 assert(!Op.isLiteral() && "Not to be used with literals!"); in skipAbbreviatedField()
80 switch (Op.getEncoding()) { in skipAbbreviatedField()
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/external/llvm/lib/CodeGen/
DMIRPrinter.cpp119 void printTargetFlags(const MachineOperand &Op);
120 void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
122 void print(const MachineMemOperand &Op);
572 for (const auto *Op : MI.memoperands()) { in print() local
575 print(*Op); in print()
669 void MIPrinter::printTargetFlags(const MachineOperand &Op) { in printTargetFlags() argument
670 if (!Op.getTargetFlags()) in printTargetFlags()
673 Op.getParent()->getParent()->getParent()->getSubtarget().getInstrInfo(); in printTargetFlags()
675 auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags()); in printTargetFlags()
729 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI, in print() argument
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/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp58 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
321 auto Op = make_unique<SparcOperand>(k_Token); in CreateToken() local
322 Op->Tok.Data = Str.data(); in CreateToken()
323 Op->Tok.Length = Str.size(); in CreateToken()
324 Op->StartLoc = S; in CreateToken()
325 Op->EndLoc = S; in CreateToken()
326 return Op; in CreateToken()
331 auto Op = make_unique<SparcOperand>(k_Register); in CreateReg() local
332 Op->Reg.RegNum = RegNum; in CreateReg()
333 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind; in CreateReg()
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h123 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
125 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h484 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
503 void computeKnownBitsForTargetNode(const SDValue Op,
552 void LowerAsmOperandForConstraint(SDValue Op,
689 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
695 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
697 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
699 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
720 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
721 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
722 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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