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Searched refs:isReg (Results 1 – 25 of 206) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DMachineOperand.h192 return isReg() ? 0 : SubReg_TargetFlags; in getTargetFlags()
195 assert(!isReg() && "Register operands can't have target flags"); in setTargetFlags()
200 assert(!isReg() && "Register operands can't have target flags"); in addTargetFlag()
230 bool isReg() const { return OpKind == MO_Register; } in isReg() function
268 assert(isReg() && "This is not a register operand!"); in getReg()
273 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg()
278 assert(isReg() && "Wrong MachineOperand accessor"); in isUse()
283 assert(isReg() && "Wrong MachineOperand accessor"); in isDef()
288 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit()
293 assert(isReg() && "Wrong MachineOperand accessor"); in isDead()
[all …]
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { in isReg() function
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); in isReg()
192 if (Op.isReg()) { in printOperand()
299 return (isReg<Mips::ZERO>(MI, 0) && isReg<Mips::ZERO>(MI, 1) && in printAlias()
301 (isReg<Mips::ZERO>(MI, 1) && printAlias("beqz", MI, 0, 2, OS)); in printAlias()
304 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); in printAlias()
307 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
310 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); in printAlias()
313 return isReg<Mips::ZERO>(MI, 0) && printAlias("bal", MI, 1, OS); in printAlias()
316 return isReg<Mips::FCC0>(MI, 0) && printAlias("bc1t", MI, 1, OS); in printAlias()
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
220 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding()
239 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding()
259 assert(MI.getOperand(OpNo+1).isReg()); in getSPE8DisEncoding()
275 assert(MI.getOperand(OpNo+1).isReg()); in getSPE4DisEncoding()
291 assert(MI.getOperand(OpNo+1).isReg()); in getSPE2DisEncoding()
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/external/llvm/lib/CodeGen/
DMachineInstr.cpp99 assert(isReg() && "Wrong MachineOperand accessor"); in setIsDef()
119 if (!isReg() || !isOnRegUseList()) in removeRegFromUses()
134 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToImmediate()
143 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm"); in ChangeToFPImmediate()
152 assert((!isReg() || !isTied()) && in ChangeToES()
164 assert((!isReg() || !isTied()) && in ChangeToMCSymbol()
186 bool WasReg = isReg(); in ChangeToRegister()
698 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
707 if (MO.isReg()) in AddRegOperandsToUseLists()
754 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand()
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DLivePhysRegs.cpp47 if (O->isReg()) { in stepBackward()
60 if (!O->isReg() || !O->readsReg() || O->isUndef()) in stepBackward()
77 if (O->isReg()) { in stepForward()
98 if (Reg.second->isReg() && Reg.second->isDead()) in stepForward()
DDeadMachineInstructionElim.cpp74 if (MO.isReg() && MO.isDef()) { in isDead()
140 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
159 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
DMachineLICM.cpp376 if (!MO.isReg()) in ProcessMI()
481 if (!MO.isReg()) in HoistRegionPostRA()
510 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA()
540 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns()
729 if (!MO.isDef() || !MO.isReg() || !MO.getReg()) in SinkIntoLoop()
812 if (!MO.isReg() || MO.isImplicit()) in calcRegisterCost()
895 if (!MO.isReg()) in IsLoopInvariantInst()
945 if (!MO.isReg() || !MO.isDef()) in HasLoopPHIUse()
987 if (!MO.isReg() || !MO.isUse()) in HasHighOperandLatency()
1014 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
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/external/llvm/lib/Target/AMDGPU/
DSIFoldOperands.cpp67 assert(FoldOp->isReg()); in FoldCandidate()
111 assert(Old.isReg()); in updateOperand()
183 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() || in tryAddToFoldList()
184 !MI->getOperand(CommuteIdx1).isReg())) in tryAddToFoldList()
208 if (UseOp.isReg() && ((UseOp.getSubReg() && OpToFold.isReg()) || in foldOperand()
327 if (!FoldingImm && !OpToFold.isReg()) in runOnMachineFunction()
338 if (OpToFold.isReg() && in runOnMachineFunction()
368 assert(Fold.OpToFold && Fold.OpToFold->isReg()); in runOnMachineFunction()
DSIInstrInfo.cpp818 assert(SrcOp.isReg()); in expandPostRAPseudo()
899 if (!Src0.isReg()) in commuteInstructionImpl()
927 if (!Src1.isReg()) { in commuteInstructionImpl()
989 if (!MI->getOperand(Src0Idx).isReg()) in findCommutedOpIndices()
1002 } else if (Src1.isReg()) { in findCommutedOpIndices()
1068 if (Src0->isReg() && Src0->getReg() == Reg) { in FoldImmediate()
1069 if (!Src1->isReg() || in FoldImmediate()
1070 (Src1->isReg() && RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))) in FoldImmediate()
1073 if (!Src2->isReg() || in FoldImmediate()
1074 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))) in FoldImmediate()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonVLIWPacketizer.cpp115 if (!MO.isReg() || !MO.isDef()) in hasWriteToReadDep()
283 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) in isCallDependent()
351 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg()) in cleanUpDotCur()
391 if (MO.isReg() && MO.getReg() == DestReg) in canPromoteToDotCur()
457 if (MO.isReg() && MO.isDef()) in getPostIncrementOperand()
461 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg())) in getPostIncrementOperand()
467 assert(Op1.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
473 assert(Op0.isReg() && "Post increment operand has be to a register."); in getPostIncrementOperand()
532 if (Val.isReg() && Val.getReg() != DepReg) in canPromoteToNewValueStore()
585 if (!MO.isReg()) in canPromoteToNewValueStore()
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DHexagonExpandCondsets.cpp277 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) in makeDefined()
309 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg) in makeUndead()
337 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg) in shrinkToUses()
366 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) in updateKillFlags()
437 if (Op.isReg() && Op.isDef()) in addInstrToLiveness()
514 if (!Op.isReg() || !Op.isUse() || Op.isImplicit() || Op.isUndef()) in addInstrToLiveness()
553 if (!Op.isReg() || !Op.isDef()) in removeInstrFromLiveness()
631 if (!Op.isReg() || !Op.isUse()) in removeInstrFromLiveness()
652 if (SO.isReg()) { in getCondTfrOpcode()
758 if (!Op.isReg() || !Op.isDef()) in isPredicable()
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DHexagonHardwareLoops.cpp312 bool isReg() const { return Kind == CV_Register; } in isReg() function in __anonfb58bf460111::CountValue
316 assert(isReg() && "Wrong CountValue accessor"); in getReg()
320 assert(isReg() && "Wrong CountValue accessor"); in getSubReg()
329 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); } in print()
642 if (Op1.isReg()) { in getLoopTripCount()
662 if (InitialValue->isReg()) { in getLoopTripCount()
669 if (EndValue->isReg()) { in getLoopTripCount()
696 if (Start->isReg()) { in computeCount()
702 if (End->isReg()) { in computeCount()
709 if (!Start->isReg() && !Start->isImm()) in computeCount()
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DHexagonSplitDouble.cpp113 assert(R.isReg()); in getRegState()
169 if (MI->getOperand(1).isReg()) in isFixedInstr()
174 if (MI->getOperand(0).isReg()) in isFixedInstr()
201 if (!Op.isReg()) in isFixedInstr()
250 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
410 if (Op.isReg() && Part.count(Op.getReg())) in isProfitable()
467 assert(Cond[1].isReg() && "Unexpected Cond vector from AnalyzeBranch"); in collectIndRegsForLoop()
568 if (!Op.isReg()) { in createHalfInstr()
673 assert(Op0.isReg() && Op1.isImm()); in splitImmediate()
702 assert(Op0.isReg()); in splitCombine()
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DHexagonNewValueJump.cpp152 if (II->getOperand(i).isReg() && in INITIALIZE_PASS_DEPENDENCY()
506 MI->getOperand(0).isReg() && in runOnMachineFunction()
514 isSecondOpReg = MI->getOperand(2).isReg(); in runOnMachineFunction()
548 if (MI->getOperand(0).isReg() && in runOnMachineFunction()
605 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
612 if (localMO.isReg() && localMO.isUse() && in runOnMachineFunction()
667 if (cmpInstr->getOperand(0).isReg() && in runOnMachineFunction()
670 if (cmpInstr->getOperand(1).isReg() && in runOnMachineFunction()
DHexagonAsmPrinter.cpp149 if (!MI->getOperand(OpNo).isReg() || in PrintAsmOperand()
151 !MI->getOperand(OpNo+1).isReg()) in PrintAsmOperand()
178 if (Base.isReg()) in PrintAsmMemoryOperand()
321 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
332 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
344 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
356 assert (Rs.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
538 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
550 assert (Inst.getOperand(0).isReg() && in HexagonProcessInstruction()
DHexagonCopyToCombine.cpp122 assert(Op0.isReg() && Op1.isReg()); in isCombinableInstType()
135 assert(Op0.isReg()); in isCombinableInstType()
197 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill()) in removeKillInfo()
216 return MO.isReg() ? MO.getReg() : 0; in UseReg()
355 if (!Op.isReg() || !Op.isUse() || !Op.getReg()) in findPotentialNewifiableTFRs()
385 if (!Op.isReg() || !Op.isDef() || !Op.getReg()) in findPotentialNewifiableTFRs()
524 bool IsHiReg = HiOperand.isReg(); in combine()
525 bool IsLoReg = LoOperand.isReg(); in combine()
DHexagonGenMux.cpp132 if (!Mo->isReg() || Mo->isImplicit()) in getDefsUses()
173 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
263 unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0; in genMuxInBlock()
264 unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0; in genMuxInBlock()
/external/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcMCCodeEmitter.cpp119 if (MO.isReg()) in getMachineOpValue()
146 if (MO.isReg() || MO.isImm()) in getCallTargetOpValue()
181 if (MO.isReg() || MO.isImm()) in getBranchTargetOpValue()
194 if (MO.isReg() || MO.isImm()) in getBranchPredTargetOpValue()
206 if (MO.isReg() || MO.isImm()) in getBranchOnRegTargetOpValue()
/external/llvm/lib/Target/Sparc/InstPrinter/
DSparcInstPrinter.cpp62 if (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
86 || (!MI->getOperand(0).isReg()) in printSparcAliasInstr()
112 if (MO.isReg()) { in printOperand()
139 if (MO.isReg() && MO.getReg() == SP::G0) in printMemOperand()
/external/llvm/lib/Target/SystemZ/AsmParser/
DSystemZAsmParser.cpp196 bool isReg() const override { in isReg() function in __anon920606c00111::SystemZOperand
199 bool isReg(RegisterKind RegKind) const { in isReg() function in __anon920606c00111::SystemZOperand
310 bool isGR32() const { return isReg(GR32Reg); } in isGR32()
311 bool isGRH32() const { return isReg(GRH32Reg); } in isGRH32()
313 bool isGR64() const { return isReg(GR64Reg); } in isGR64()
314 bool isGR128() const { return isReg(GR128Reg); } in isGR128()
315 bool isADDR32() const { return isReg(ADDR32Reg); } in isADDR32()
316 bool isADDR64() const { return isReg(ADDR64Reg); } in isADDR64()
318 bool isFP32() const { return isReg(FP32Reg); } in isFP32()
319 bool isFP64() const { return isReg(FP64Reg); } in isFP64()
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/external/llvm/lib/Target/AArch64/
DAArch64AsmPrinter.cpp141 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm()) in getDebugValueLocation()
240 assert(MO.isReg() && "Should only get here with a register!"); in printAsmRegInClass()
270 if (MO.isReg()) in PrintAsmOperand()
284 if (MO.isReg()) { in PrintAsmOperand()
314 if (MO.isReg()) { in PrintAsmOperand()
340 assert(MO.isReg() && "unexpected inline asm memory operand"); in PrintAsmMemoryOperand()
355 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm()); in PrintDebugValueComment()
/external/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp112 if (isReg()) in addRegOrImmOperands()
178 bool isReg() const override { in isReg() function in __anon2fa8e53e0111::AMDGPUOperand
187 assert(isReg()); in setModifiers()
201 return isReg() || isImm(); in isRegOrImm()
209 return isInlineImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID)); in isSCSrc32()
213 return isImm() || (isReg() && isRegClass(AMDGPU::SReg_32RegClassID)); in isSSrc32()
218 (isReg() && isRegClass(AMDGPU::SReg_64RegClassID)); in isSSrc64()
222 return (isReg() && isRegClass(AMDGPU::SReg_64RegClassID)) || isInlineImm(); in isSCSrc64()
226 return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_32RegClassID)); in isVCSrc32()
230 return isInlineImm() || (isReg() && isRegClass(AMDGPU::VS_64RegClassID)); in isVCSrc64()
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/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp648 if (MO.isReg()) { in getMachineOpValue()
670 assert(MI.getOperand(OpNo).isReg()); in getMSAMemEncoding()
714 assert(MI.getOperand(OpNo).isReg()); in getMemEncoding()
726 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4()
740 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl1()
754 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm4Lsl2()
768 assert(MI.getOperand(OpNo).isReg() && in getMemEncodingMMSPImm5Lsl2()
783 assert(MI.getOperand(OpNo).isReg() && in getMemEncodingMMGPImm7Lsl2()
798 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm9()
822 assert(MI.getOperand(OpNo).isReg()); in getMemEncodingMMImm12()
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/external/llvm/lib/MC/
DMCInstrDesc.cpp47 if (MI.getOperand(i).isReg() && in mayAffectControlFlow()
66 if (MI.getOperand(i).isReg() && in hasDefOfPhysReg()
/external/llvm/include/llvm/MC/
DMCInst.h56 bool isReg() const { return Kind == kRegister; } in isReg() function
64 assert(isReg() && "This is not a register operand!"); in getReg()
70 assert(isReg() && "This is not a register operand!"); in setReg()

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