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Searched refs:DestReg (Results 1 – 25 of 84) sorted by relevance

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/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp42 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
48 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
52 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
53 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
66 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
98 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
102 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
103 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()
106 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
107 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
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DThumbRegisterInfo.cpp64 DebugLoc dl, unsigned DestReg, in emitThumb1LoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
84 DebugLoc dl, unsigned DestReg, in emitThumb2LoadConstPool() argument
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, in emitLoadConstPool() argument
110 assert((isARMLowRegister(DestReg) || isVirtualRegister(DestReg)) && in emitLoadConstPool()
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
127 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg() argument
133 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
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DThumb2InstrInfo.cpp114 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
167 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
181 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
191 MRI->constrainRegClass(DestReg, &ARM::GPRPair_with_gsub_1_in_rGPRRegClass); in loadRegFromStackSlot()
194 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
195 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
199 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
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DARMBaseInstrInfo.cpp661 unsigned DestReg, bool KillSrc, in copyFromCPSR() argument
668 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg); in copyFromCPSR()
704 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
706 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
710 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
715 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
725 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP()) in copyPhysReg()
727 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
731 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
745 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
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DARMBaseInstrInfo.h174 unsigned DestReg, bool KillSrc,
178 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
189 unsigned DestReg, int FrameIndex,
196 unsigned DestReg, unsigned SubIdx,
470 unsigned DestReg, unsigned BaseReg, int NumBytes,
476 unsigned DestReg, unsigned BaseReg, int NumBytes,
481 unsigned DestReg, unsigned BaseReg,
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp282 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
296 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
297 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
299 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
304 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
305 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
307 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
309 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
317 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
320 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
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/external/llvm/lib/Target/Hexagon/
DHexagonSplitConst32AndConst64.cpp93 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
97 TII->get(Hexagon::LO), DestReg).addOperand(Symbol); in runOnMachineFunction()
99 TII->get(Hexagon::HI), DestReg).addOperand(Symbol); in runOnMachineFunction()
108 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
121 TII->get(Hexagon::A2_tfrsi), DestReg).addImm(ImmValue); in runOnMachineFunction()
127 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
139 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg); in runOnMachineFunction()
140 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg); in runOnMachineFunction()
DHexagonCopyToCombine.cpp94 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
97 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
100 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
103 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
124 unsigned DestReg = Op0.getReg(); in isCombinableInstType() local
126 return Hexagon::IntRegsRegClass.contains(DestReg) && in isCombinableInstType()
137 unsigned DestReg = Op0.getReg(); in isCombinableInstType() local
146 return Hexagon::IntRegsRegClass.contains(DestReg) && in isCombinableInstType()
206 unsigned DestReg, in isUnsafeToMoveAcross() argument
209 I->modifiesRegister(DestReg, TRI) || in isUnsafeToMoveAcross()
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/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp81 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
115 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
117 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
119 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
120 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
121 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
122 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
123 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
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DMipsFastISel.cpp119 bool emitCmp(unsigned DestReg, const CmpInst *CI);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
134 unsigned DestReg);
136 unsigned DestReg);
334 unsigned DestReg = createResultReg(RC); in materializeFP() local
336 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
337 return DestReg; in materializeFP()
340 unsigned DestReg = createResultReg(RC); in materializeFP() local
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DMips16InstrInfo.cpp63 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
67 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
70 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
74 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
78 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
86 if (DestReg) in copyPhysReg()
87 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
113 unsigned DestReg, int FI, in loadRegFromStack() argument
125 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) in loadRegFromStack()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp1516 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, in forwardCopyWillClobberTuple() argument
1520 return ((DestReg - SrcReg) & 0x1f) < NumRegs; in forwardCopyWillClobberTuple()
1525 unsigned DestReg, unsigned SrcReg, bool KillSrc, unsigned Opcode, in copyPhysRegTuple() argument
1530 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyPhysRegTuple()
1543 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyPhysRegTuple()
1551 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
1553 if (AArch64::GPR32spRegClass.contains(DestReg) && in copyPhysReg()
1557 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { in copyPhysReg()
1561 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32, in copyPhysReg()
1575 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg) in copyPhysReg()
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DAArch64A57FPLoadBalancing.cpp627 unsigned DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
630 << TRI->getName(DestReg) << " at " << *MI); in scanInstruction()
632 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
633 ActiveChains[DestReg] = G.get(); in scanInstruction()
640 unsigned DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
645 if (DestReg != AccumReg) in scanInstruction()
660 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
662 if (DestReg != AccumReg) { in scanInstruction()
663 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
675 << TRI->getName(DestReg) << "\n"); in scanInstruction()
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/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp275 unsigned DestReg = MI->getOperand(0).getReg(); in getAluKind() local
276 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) || in getAluKind()
277 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass)) in getAluKind()
279 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass)) in getAluKind()
281 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass)) in getAluKind()
283 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass)) in getAluKind()
285 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass)) in getAluKind()
364 unsigned DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
371 MO.getReg() == DestReg) in AssignSlot()
377 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass); in AssignSlot()
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/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp725 unsigned DestReg, ArrayRef<MachineOperand> Cond, in insertSelect() argument
782 BuildMI(MBB, MI, dl, get(OpCode), DestReg) in insertSelect()
816 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
821 if (PPC::F8RCRegClass.contains(DestReg) && in copyPhysReg()
824 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass); in copyPhysReg()
829 DestReg = SuperReg; in copyPhysReg()
830 } else if (PPC::VRRCRegClass.contains(DestReg) && in copyPhysReg()
833 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass); in copyPhysReg()
838 DestReg = SuperReg; in copyPhysReg()
840 PPC::VSRCRegClass.contains(DestReg)) { in copyPhysReg()
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DPPCRegisterInfo.cpp523 unsigned DestReg = MI.getOperand(0).getReg(); in lowerCRRestore() local
524 assert(MI.definesRegister(DestReg) && in lowerCRRestore()
532 if (DestReg != PPC::CR0) { in lowerCRRestore()
536 unsigned ShiftBits = getEncodingValue(DestReg)*4; in lowerCRRestore()
543 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) in lowerCRRestore()
610 unsigned DestReg = MI.getOperand(0).getReg(); in lowerCRBitRestore() local
611 assert(MI.definesRegister(DestReg) && in lowerCRBitRestore()
617 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); in lowerCRBitRestore()
621 .addReg(getCRFromCRBit(DestReg)); in lowerCRBitRestore()
623 unsigned ShiftBits = getEncodingValue(DestReg); in lowerCRBitRestore()
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DPPCFastISel.cpp155 bool isZExt, unsigned DestReg);
164 unsigned DestReg, bool IsZExt);
801 bool IsZExt, unsigned DestReg) { in PPCEmitCmp() argument
885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) in PPCEmitCmp()
888 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) in PPCEmitCmp()
926 unsigned DestReg = createResultReg(&PPC::F4RCRegClass); in SelectFPTrunc() local
927 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg) in SelectFPTrunc()
930 updateValueMap(I, DestReg); in SelectFPTrunc()
1039 unsigned DestReg = createResultReg(RC); in SelectIToFP() local
1048 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) in SelectIToFP()
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/external/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp36 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
38 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
65 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
73 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp125 unsigned DestReg = MI->getOperand(0).getReg(); in expandRIEPseudo() local
127 bool DestIsHigh = isHighReg(DestReg); in expandRIEPseudo()
133 DestReg, SrcReg, SystemZ::LR, 32, in expandRIEPseudo()
136 MI->getOperand(1).setReg(DestReg); in expandRIEPseudo()
170 DebugLoc DL, unsigned DestReg, in emitGRX32Move() argument
174 bool DestIsHigh = isHighReg(DestReg); in emitGRX32Move()
183 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg) in emitGRX32Move()
188 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move()
189 .addReg(DestReg, RegState::Undef) in emitGRX32Move()
553 DebugLoc DL, unsigned DestReg, in copyPhysReg() argument
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/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h244 unsigned DestReg) { in BuildMI() argument
246 .addReg(DestReg, RegState::Define); in BuildMI()
256 unsigned DestReg) { in BuildMI() argument
260 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
267 unsigned DestReg) { in BuildMI() argument
271 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
278 unsigned DestReg) { in BuildMI() argument
281 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
285 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
338 unsigned DestReg) { in BuildMI() argument
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/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp66 unsigned DestReg, int FrameIdx, in loadRegFromStackSlot() argument
81 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
84 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
91 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
94 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
96 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
101 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.cpp39 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
46 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); in copyPhysReg()
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) in copyPhysReg()
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInfo.cpp37 DebugLoc DL, unsigned DestReg, in copyPhysReg() argument
42 const TargetRegisterClass *RC = TargetRegisterInfo::isVirtualRegister(DestReg) ? in copyPhysReg()
43 MRI.getRegClass(DestReg) : in copyPhysReg()
58 BuildMI(MBB, I, DL, get(CopyLocalOpcode), DestReg) in copyPhysReg()
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp35 unsigned DestReg, unsigned SrcReg, bool KillSrc) const { in copyPhysReg() argument
37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg); in copyPhysReg()
63 BuildMI(MBB, I, DL, get(Op), DestReg) in copyPhysReg()
68 unsigned &DestReg) const { in isMoveInstr()
83 DestReg = dest.getReg(); in isMoveInstr()
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp334 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
336 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); in copyPhysReg()
340 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) in copyPhysReg()
347 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); in copyPhysReg()
351 if (DestReg == XCore::SP && GRSrc) { in copyPhysReg()
384 unsigned DestReg, int FrameIndex, in loadRegFromStackSlot() argument
397 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) in loadRegFromStackSlot()

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