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Searched refs:getRegClassFor (Results 1 – 25 of 67) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp95 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
132 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
328 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
329 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
339 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
340 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
476 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
487 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
DInstrEmitter.cpp109 UseRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
168 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
230 TLI->getRegClassFor(Node->getSimpleValueType(i)); in CreateVirtualRegisters()
294 TLI->getRegClassFor(Op.getSimpleValueType()); in getVR()
400 TLI->isTypeLegal(OpVT) ? TLI->getRegClassFor(OpVT) : nullptr; in AddOperand()
483 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
518 TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
588 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
DFunctionLoweringInfo.cpp357 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT)); in CreateReg()
540 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateSwiftErrorVReg()
559 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateSwiftErrorVRegDefAt()
DFastISel.cpp444 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeConstant()
932 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); in selectPatchpoint()
1524 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1525 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
2191 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in fastEmitInst_extractsubreg()
/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp98 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
136 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
336 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
337 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
347 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
348 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
500 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
DInstrEmitter.cpp109 UseRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
167 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
229 TLI->getRegClassFor(Node->getSimpleValueType(i)); in CreateVirtualRegisters()
294 TLI->getRegClassFor(Op.getSimpleValueType()); in getVR()
460 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
495 TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
550 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
DFastISel.cpp257 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeConstant()
756 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); in selectPatchpoint()
1306 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1307 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
1998 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in fastEmitInst_extractsubreg()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFastISel.cpp464 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in FastEmitInst_extractsubreg()
478 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
488 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
514 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
531 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
547 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
608 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
625 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
672 TargetRegisterClass* RC = TLI.getRegClassFor(VT); in TargetMaterializeAlloca()
939 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
[all …]
DARMISelLowering.h341 virtual TargetRegisterClass *getRegClassFor(EVT VT) const;
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp408 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
418 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
444 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
460 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
525 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
614 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
628 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
679 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
984 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
995 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMFastISel.cpp404 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
414 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
440 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
456 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
520 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
613 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
627 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
678 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
984 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
995 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp89 UseRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
147 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
255 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); in getVR()
416 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
452 const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0)); in EmitSubregNode()
505 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0)); in EmitSubregNode()
DFastISel.cpp207 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeRegForValue()
592 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in SelectCall()
616 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); in SelectCall()
729 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); in SelectBitCast()
730 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); in SelectBitCast()
1300 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in FastEmitInst_extractsubreg()
DFunctionLoweringInfo.cpp209 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); in CreateReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86FastISel.cpp2040 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
2228 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect()
2365 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect()
2393 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect()
2463 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); in X86SelectIntToFP()
2640 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); in fastLowerIntrinsicCall()
2852 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in fastLowerIntrinsicCall()
2942 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
2975 TLI.getRegClassFor(VT), RHSReg, RHSIsKill); in fastLowerIntrinsicCall()
2985 ResultReg = fastEmitInst_r(MULOpc[0], TLI.getRegClassFor(VT), RHSReg, in fastLowerIntrinsicCall()
[all …]
/external/llvm/lib/Target/X86/
DX86FastISel.cpp1946 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
2122 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect()
2216 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect()
2244 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect()
2462 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); in fastLowerIntrinsicCall()
2759 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
2792 TLI.getRegClassFor(VT), RHSReg, RHSIsKill); in fastLowerIntrinsicCall()
2802 ResultReg = fastEmitInst_r(MULOpc[0], TLI.getRegClassFor(VT), RHSReg, in fastLowerIntrinsicCall()
2806 TLI.getRegClassFor(VT), LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
2880 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Nios2/
DNios2ISelLowering.cpp112 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1110 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicBinary()
1214 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1234 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1237 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicBinaryPartword()
1398 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicCmpSwap()
1488 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
1491 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicCmpSwapPartword()
2131 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
3082 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3150 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); in LowerFormalArguments()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1539 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1558 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1561 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicBinaryPartword()
1715 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicCmpSwap()
1769 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
1772 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicCmpSwapPartword()
2324 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
3376 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3443 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32)); in LowerFormalArguments()
3781 RC = getRegClassFor(VT); in parseRegForInlineAsmConstraint()
[all …]
/external/llvm/lib/CodeGen/
DCallingConvLower.cpp245 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DCallingConvLower.cpp262 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXISelLowering.cpp239 TargetRegisterClass* TRC = getRegClassFor(RegVT); in LowerFormalArguments()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsISelLowering.cpp882 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in EmitAtomicBinary()
955 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in EmitAtomicBinaryPartword()
1107 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in EmitAtomicCmpSwap()
1175 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in EmitAtomicCmpSwapPartword()
2368 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); in LowerFormalArguments()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp416 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
429 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
449 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
535 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
2903 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP()
3133 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
3570 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3736 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp370 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
403 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
488 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
2814 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP()
3047 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
3484 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3650 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()

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