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/external/elfutils/tests/
Drun-allregs.sh32 0: %eax (eax), signed 32 bits
33 1: %ecx (ecx), signed 32 bits
34 2: %edx (edx), signed 32 bits
35 3: %ebx (ebx), signed 32 bits
36 4: %esp (esp), address 32 bits
37 5: %ebp (ebp), address 32 bits
38 6: %esi (esi), signed 32 bits
39 7: %edi (edi), signed 32 bits
40 8: %eip (eip), address 32 bits
41 9: %eflags (eflags), unsigned 32 bits
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepInstrFormats.td12 bits <5> Rs32;
14 bits <5> Rd32;
18 bits <5> Rss32;
20 bits <5> Rdd32;
24 bits <5> Rs32;
26 bits <5> Rt32;
28 bits <5> Rd32;
32 bits <5> Rt32;
34 bits <5> Rs32;
36 bits <5> Rd32;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrFormats.td12 bits <5> Rs32;
14 bits <5> Rd32;
16 bits <2> Pe4;
20 bits <2> Qs4;
22 bits <5> Rt32;
24 bits <1> Mu2;
26 bits <5> Vv32;
28 bits <5> Vw32;
32 bits <2> Ps4;
34 bits <2> Pt4;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td47 field bits<16> Inst;
48 field bits<16> SoftFail = 0;
49 bits<6> Opcode = 0x0;
57 bits<3> rd;
58 bits<3> rt;
59 bits<3> rs;
61 bits<16> Inst;
70 class ANDI_FM_MM16<bits<6> funct> {
71 bits<3> rd;
72 bits<3> rs;
[all …]
DMipsMSAInstrFormats.td30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 bits<5> ws;
32 bits<5> wd;
33 bits<3> m;
43 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
44 bits<5> ws;
45 bits<5> wd;
46 bits<4> m;
56 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
57 bits<5> ws;
[all …]
DMicroMips32r6InstrFormats.td38 bits<10> offset;
40 bits<16> Inst;
46 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> {
47 bits<3> rs;
48 bits<7> offset;
50 bits<16> Inst;
57 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
58 bits<5> rs;
60 bits<16> Inst;
68 bits<5> rt;
[all …]
DMipsInstrFormats.td26 class Format<bits<4> val> {
27 bits<4> Value = val;
74 field bits<32> Inst;
81 bits<6> Opcode = 0;
83 // Top 6 bits are the 'opcode' field
96 bits<4> FormBits = Form.Value;
111 field bits<32> SoftFail = 0;
151 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
155 bits<5> rd;
156 bits<5> rs;
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td47 field bits<16> Inst;
48 field bits<16> SoftFail = 0;
49 bits<6> Opcode = 0x0;
57 bits<3> rd;
58 bits<3> rt;
59 bits<3> rs;
61 bits<16> Inst;
70 class ANDI_FM_MM16<bits<6> funct> {
71 bits<3> rd;
72 bits<3> rs;
[all …]
DMipsMSAInstrFormats.td30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 bits<5> ws;
32 bits<5> wd;
33 bits<3> m;
43 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
44 bits<5> ws;
45 bits<5> wd;
46 bits<4> m;
56 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
57 bits<5> ws;
[all …]
DMicroMips32r6InstrFormats.td38 bits<10> offset;
40 bits<16> Inst;
46 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> {
47 bits<3> rs;
48 bits<7> offset;
50 bits<16> Inst;
57 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
58 bits<5> rs;
60 bits<16> Inst;
68 bits<5> rt;
[all …]
DMipsInstrFormats.td26 class Format<bits<4> val> {
27 bits<4> Value = val;
74 field bits<32> Inst;
81 bits<6> Opcode = 0;
83 // Top 6 bits are the 'opcode' field
96 bits<4> FormBits = Form.Value;
111 field bits<32> SoftFail = 0;
151 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
155 bits<5> rd;
156 bits<5> rs;
[all …]
/external/llvm/lib/Target/Mips/
DMicroMipsInstrFormats.td35 field bits<16> Inst;
36 field bits<16> SoftFail = 0;
37 bits<6> Opcode = 0x0;
45 bits<3> rd;
46 bits<3> rt;
47 bits<3> rs;
49 bits<16> Inst;
58 class ANDI_FM_MM16<bits<6> funct> {
59 bits<3> rd;
60 bits<3> rs;
[all …]
DMicroMips32r6InstrFormats.td45 bits<10> offset;
47 bits<16> Inst;
53 class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
54 bits<3> rs;
55 bits<7> offset;
57 bits<16> Inst;
64 class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
65 bits<5> rs;
67 bits<16> Inst;
75 bits<5> rt;
[all …]
DMipsMSAInstrFormats.td30 class MSA_BIT_B_FMT<bits<3> major, bits<6> minor>: MSAInst {
31 bits<5> ws;
32 bits<5> wd;
33 bits<3> m;
43 class MSA_BIT_H_FMT<bits<3> major, bits<6> minor>: MSAInst {
44 bits<5> ws;
45 bits<5> wd;
46 bits<4> m;
56 class MSA_BIT_W_FMT<bits<3> major, bits<6> minor>: MSAInst {
57 bits<5> ws;
[all …]
DMipsInstrFormats.td27 class Format<bits<4> val> {
28 bits<4> Value = val;
75 field bits<32> Inst;
82 bits<6> Opcode = 0;
84 // Top 6 bits are the 'opcode' field
97 bits<4> FormBits = Form.Value;
109 field bits<32> SoftFail = 0;
148 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
152 bits<5> rd;
153 bits<5> rs;
[all …]
DMicroMips64r6InstrFormats.td15 bits<5> rt;
16 bits<5> rs;
17 bits<16> imm;
19 bits<32> Inst;
27 class POOL32I_ADD_IMM_FM_MMR6<bits<5> funct> {
28 bits<5> rs;
29 bits<16> imm;
31 bits<32> Inst;
39 class POOL32S_EXTBITS_FM_MMR6<bits<6> funct> {
40 bits<5> rt;
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td18 field bits<64> Inst;
22 bits<2> FlagOperandIdx = 0;
68 field bits<32> Word0;
70 bits<11> src0;
71 bits<1> src0_rel;
72 bits<11> src1;
73 bits<1> src1_rel;
74 bits<3> index_mode = 0;
75 bits<2> pred_sel;
76 bits<1> last;
[all …]
DVIInstrFormats.td14 class DSe_vi <bits<8> op> : Enc64 {
15 bits<8> vdst;
16 bits<1> gds;
17 bits<8> addr;
18 bits<8> data0;
19 bits<8> data1;
20 bits<8> offset0;
21 bits<8> offset1;
34 class MUBUFe_vi <bits<7> op> : Enc64 {
35 bits<12> offset;
[all …]
/external/llvm/test/TableGen/
DBitsInit.td6 bits<2> opc = { 0, 1 };
7 bits<2> opc2 = { 1, 0 };
8 bits<1> opc3 = { 1 };
9 bits<2> a = { opc, opc2 }; // error!
10 bits<2> b = { opc{0}, opc2{0} };
11 bits<2> c = { opc{1}, opc2{1} };
12 bits<2> c = { opc3{0}, opc3 };
16 // CHECK: bits<2> opc = { 0, 1 };
17 // CHECK: bits<2> opc2 = { 1, 0 };
18 // CHECK: bits<1> opc3 = { 1 };
[all …]
/external/llvm-project/llvm/test/TableGen/
DBitsInit.td6 bits<2> opc = { 0, 1 };
7 bits<2> opc2 = { 1, 0 };
8 bits<1> opc3 = { 1 };
9 bits<2> a = { opc, opc2 }; // error!
10 bits<2> b = { opc{0}, opc2{0} };
11 bits<2> c = { opc{1}, opc2{1} };
12 bits<2> c = { opc3{0}, opc3 };
16 // CHECK: bits<2> opc = { 0, 1 };
17 // CHECK: bits<2> opc2 = { 1, 0 };
18 // CHECK: bits<1> opc3 = { 1 };
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td26 field bits<64> Inst;
30 bits<2> FlagOperandIdx = 0;
77 field bits<32> Word0;
79 bits<11> src0;
80 bits<1> src0_rel;
81 bits<11> src1;
82 bits<1> src1_rel;
83 bits<3> index_mode = 0;
84 bits<2> pred_sel;
85 bits<1> last;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600InstrFormats.td26 field bits<64> Inst;
30 bits<2> FlagOperandIdx = 0;
77 field bits<32> Word0;
79 bits<11> src0;
80 bits<1> src0_rel;
81 bits<11> src1;
82 bits<1> src1_rel;
83 bits<3> index_mode = 0;
84 bits<2> pred_sel;
85 bits<1> last;
[all …]
/external/mesa3d/prebuilt-intermediates/bifrost/
Dbifrost_gen_disasm.c3 #define _BITS(bits, pos, width) (((bits) >> (pos)) & ((1 << (width)) - 1)) argument
5 bi_disasm_add_ld_var_special_1(FILE *fp, unsigned bits, struct bifrost_regs *srcs, struct bifrost_r… in bi_disasm_add_ld_var_special_1() argument
10 …const char *register_format = register_format_table[(_BITS(bits, 3, 2) << 0) | (_BITS(bits, 10, 4)… in bi_disasm_add_ld_var_special_1()
14 const char *vecsize = vecsize_table[(_BITS(bits, 3, 2) << 0) | (_BITS(bits, 10, 4) << 2)]; in bi_disasm_add_ld_var_special_1()
18 …const char *varying_name = varying_name_table[(_BITS(bits, 3, 2) << 0) | (_BITS(bits, 10, 4) << 2)… in bi_disasm_add_ld_var_special_1()
22 const char *update = update_table[(_BITS(bits, 3, 2) << 0) | (_BITS(bits, 10, 4) << 2)]; in bi_disasm_add_ld_var_special_1()
26 const char *sample = sample_table[(_BITS(bits, 3, 2) << 0) | (_BITS(bits, 10, 4) << 2)]; in bi_disasm_add_ld_var_special_1()
36 dump_src(fp, _BITS(bits, 0, 3), *srcs, consts, false); in bi_disasm_add_ld_var_special_1()
42 bi_disasm_add_frcp_f16(FILE *fp, unsigned bits, struct bifrost_regs *srcs, struct bifrost_regs *nex… in bi_disasm_add_frcp_f16() argument
48 const char *neg = neg_table[_BITS(bits, 3, 1)]; in bi_disasm_add_frcp_f16()
[all …]
/external/llvm-project/libc/test/utils/FPUtil/
Dx86_long_double_test.cpp22 FPBits bits(0.0l); in TEST() local
23 bits.exponent = FPBits::maxExponent; in TEST()
27 bits.mantissa = i; in TEST()
28 long double nan = bits; in TEST()
30 ASSERT_TRUE(bits.isNaN()); in TEST()
33 bits.implicitBit = 1; in TEST()
38 bits.mantissa = i; in TEST()
39 long double nan = bits; in TEST()
41 ASSERT_TRUE(bits.isNaN()); in TEST()
44 bits.exponent = 1; in TEST()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCInstrFormats.td13 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
15 field bits<32> Inst;
16 field bits<32> SoftFail = 0;
28 bits<1> PPC970_First = 0;
29 bits<1> PPC970_Single = 0;
30 bits<1> PPC970_Cracked = 0;
31 bits<3> PPC970_Unit = 0;
41 bits<1> XFormMemOp = 0;
54 class PPC970_DGroup_First { bits<1> PPC970_First = 1; }
55 class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; }
[all …]

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