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/external/llvm/lib/Target/Hexagon/
DHexagonInstrAlias.td43 // Alias of: memXX($Rs+#XX) = $Rt to memXX($Rs) = $Rt
44 def : InstAlias<"memb($Rs) = $Rt",
45 (S2_storerb_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
47 def : InstAlias<"memh($Rs) = $Rt",
48 (S2_storerh_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
50 def : InstAlias<"memh($Rs) = $Rt.h",
51 (S2_storerf_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
53 def : InstAlias<"memw($Rs) = $Rt",
54 (S2_storeri_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
56 def : InstAlias<"memb($Rs) = $Rt.new",
[all …]
DHexagonInstrInfoVector.td226 : Pat <(Op Value:$Rs, I32:$Rt),
227 (MI Value:$Rs, I32:$Rt)>;
256 : Pat <(i1 (Op Value:$Rs, Value:$Rt)),
257 (MI Value:$Rs, Value:$Rt)>;
273 : Pat <(OutTy (Op InVal:$Rs, InVal:$Rt)),
274 (MI InVal:$Rs, InVal:$Rt)>;
291 (ins DoubleRegs:$Rs, DoubleRegs:$Rt),
293 [(set V2I32:$Rd, (mul V2I32:$Rs, V2I32:$Rt))]>;
297 (ins DoubleRegs:$Rx, DoubleRegs:$Rs, DoubleRegs:$Rt),
299 [(set V2I32:$Rd, (add V2I32:$Rx, (mul V2I32:$Rs, V2I32:$Rt)))],
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DHexagonIntrinsics.td37 : Pat<(IntID ImmPred:$Is, I32:$Rt),
38 (MI ImmPred:$Is, I32:$Rt)>;
45 : Pat<(IntID I32:$Rs, I64:$Rt),
46 (MI I32:$Rs, DoubleRegs:$Rt)>;
49 : Pat <(IntID I32:$Rs, I32:$Rt),
50 (MI I32:$Rs, I32:$Rt)>;
53 : Pat <(IntID I64:$Rs, I64:$Rt),
54 (MI DoubleRegs:$Rs, DoubleRegs:$Rt)>;
69 : Pat <(IntID I32:$Rs, I32:$Rt, imm:$Iu),
70 (MI I32:$Rs, I32:$Rt, imm:$Iu)>;
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DHexagonAsmPrinter.cpp320 MCOperand &Rt = Inst.getOperand(3); in HexagonProcessInstruction() local
321 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
322 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
327 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
331 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
332 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
333 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
338 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
343 MCOperand &Rt = Inst.getOperand(2); in HexagonProcessInstruction() local
344 assert (Rt.isReg() && "Expected register and none was found"); in HexagonProcessInstruction()
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DHexagonIntrinsicsV4.td33 // Rdd=vmpyhsu(Rs,Rt)[:<<1]:sat
37 // Rxx+=vmpyhsu(Rs,Rt)[:<<1]:sat
42 // Rdd=vpmpyh(Rs,Rt)
44 // Rxx[^]=vpmpyh(Rs,Rt)
48 // Rdd=pmpyw(Rs,Rt)
50 // Rxx^=pmpyw(Rs,Rt)
53 //Rxx^=asr(Rss,Rt)
55 //Rxx^=asl(Rss,Rt)
57 //Rxx^=lsr(Rss,Rt)
59 //Rxx^=lsl(Rss,Rt)
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DHexagonInstrInfoV3.td103 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
105 (i64 DoubleRegs:$Rt))))],
111 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
113 #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
116 bits<5> Rt;
122 let Inst{20-16} = !if(isMax, Rt, Rs);
123 let Inst{12-8} = !if(isMax, Rs, Rt);
218 : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
219 "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
260 : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
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DHexagonInstrInfo.td121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
122 "$Rd = "#mnemonic#"($Rs, $Rt)",
129 bits<5> Rt;
136 let Inst{20-16} = !if(OpsRev,Rt,Rs);
137 let Inst{12-8} = !if(OpsRev,Rs,Rt);
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
146 "$Rd = "#mnemonic#"($Rs, $Rt)",
156 bits<5> Rt;
163 let Inst{20-16} = !if(OpsRev,Rt,Rs);
165 let Inst{12-8} = !if(OpsRev,Rs,Rt);
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DHexagonInstrInfoV4.td131 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
165 : SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, IntRegs:$Rt),
166 "$Pd = "#mnemonic#"($Rs, $Rt)", [], "", S_3op_tc_2early_SLOT23>,
176 bits<5> Rt;
181 let Inst{12-8} = Rt;
194 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
196 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
197 def: Pat<(i1 (setne (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
199 (C2_not (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt))>;
200 def: Pat<(i1 (seteq (and (xor (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)),
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DHexagonIsetDx.td236 (ins IntRegs:$Rs, u3_1Imm:$u3_1, IntRegs:$Rt),
237 "memh($Rs + #$u3_1) = $Rt"> {
240 bits<4> Rt;
245 let Inst{3-0} = Rt;
525 (ins u5_2Imm:$u5_2, IntRegs:$Rt),
526 "memw(r29 + #$u5_2) = $Rt"> {
528 bits<4> Rt;
532 let Inst{3-0} = Rt;
625 (ins IntRegs:$Rs, u4_2Imm:$u4_2, IntRegs:$Rt),
626 "memw($Rs + #$u4_2) = $Rt"> {
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DHexagonInstrInfoV5.td32 // Rdd=vmpyb[s]u(Rs,Rt)
37 // Rxx+=vmpyb[s]u(Rs,Rt)
153 (ins IntRegs:$Rs, IntRegs:$Rt),
154 "$Rd = "#mnemonic#"($Rs, $Rt)", [],
159 bits<5> Rt;
167 let Inst{12-8} = Rt;
219 (ins IntRegs:$Rs, IntRegs:$Rt),
220 "$Rd, $Pe = sfrecipa($Rs, $Rt)">,
225 bits<5> Rt;
231 let Inst{12-8} = Rt;
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/external/llvm/test/CodeGen/Hexagon/
Dalu64.ll5 define i32 @test00(i64 %Rs, i64 %Rt) #0 {
7 %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
13 define i32 @test01(i64 %Rs, i64 %Rt) #0 {
15 %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
21 define i32 @test02(i64 %Rs, i64 %Rt) #0 {
23 %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
29 define i32 @test10(i32 %Rs, i32 %Rt) #0 {
31 %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
37 define i32 @test11(i32 %Rs, i32 %Rt) #0 {
39 %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
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Dusr-ovf-dep.ll15 define i32 @foo(i32 %Rs, i32 %Rt, i32 %Ru) #0 {
18 %1 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %Rt, i32 %Ru)
/external/eigen/Eigen/src/Geometry/
DUmeyama.h135 TransformationMatrixType Rt = TransformationMatrixType::Identity(m+1,m+1); variable
146 Rt.block(0,0,m,m).noalias() = svd.matrixU()*svd.matrixV().transpose();
149 Rt.block(0,0,m,m).noalias() = svd.matrixU() * S.asDiagonal() * svd.matrixV().transpose();
153 Rt.block(0,0,m,m).noalias() = svd.matrixU() * S.asDiagonal() * svd.matrixV().transpose();
162 Rt.col(m).head(m) = dst_mean;
163 Rt.col(m).head(m).noalias() -= c*Rt.topLeftCorner(m,m)*src_mean;
164 Rt.block(0,0,m,m) *= c;
168 Rt.col(m).head(m) = dst_mean;
169 Rt.col(m).head(m).noalias() -= Rt.topLeftCorner(m,m)*src_mean;
172 return Rt;
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td977 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii,
978 opc, ".w\t$Rt, $addr",
979 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> {
980 bits<4> Rt;
988 let Inst{15-12} = Rt;
993 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii,
994 opc, "\t$Rt, $addr",
995 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> {
996 bits<4> Rt;
1005 let Inst{15-12} = Rt;
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DARMInstrInfo.td1704 def i12: AI2ldst<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
1705 AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
1706 [(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
1707 bits<4> Rt;
1711 let Inst{15-12} = Rt;
1714 def rs : AI2ldst<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
1715 AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
1716 [(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
1717 bits<4> Rt;
1722 let Inst{15-12} = Rt;
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DARMInstrVFP.td805 (outs GPR:$Rt), (ins SPR:$Sn),
806 IIC_fpMOVSI, "vmov", "\t$Rt, $Sn",
807 [(set GPR:$Rt, (bitconvert SPR:$Sn))]> {
809 bits<4> Rt;
815 let Inst{15-12} = Rt;
827 (outs SPR:$Sn), (ins GPR:$Rt),
828 IIC_fpMOVIS, "vmov", "\t$Sn, $Rt",
829 [(set SPR:$Sn, (bitconvert GPR:$Rt))]>,
833 bits<4> Rt;
838 let Inst{15-12} = Rt;
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DARMInstrThumb.td598 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
599 "ldr", "\t$Rt, $addr",
600 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
603 bits<3> Rt;
605 let Inst{10-8} = Rt;
612 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
613 "ldr", "\t$Rt, $addr",
614 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
616 bits<3> Rt;
618 let Inst{10-8} = Rt;
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp207 MCOperand Rs, Rt; in getCompoundInsn() local
217 Rt = L.getOperand(0); in getCompoundInsn()
222 CompoundInsn->addOperand(Rt); in getCompoundInsn()
228 Rt = L.getOperand(0); in getCompoundInsn()
234 CompoundInsn->addOperand(Rt); in getCompoundInsn()
243 Rt = L.getOperand(2); in getCompoundInsn()
249 CompoundInsn->addOperand(Rt); in getCompoundInsn()
256 Rt = L.getOperand(2); in getCompoundInsn()
262 CompoundInsn->addOperand(Rt); in getCompoundInsn()
269 Rt = L.getOperand(2); in getCompoundInsn()
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/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td822 // v8.1 atomic ST<OP>(register) as aliases to "LD<OP>(register) when Rt=xZR"
1448 [(set GPR64:$Rt,
1451 [(set GPR32:$Rt,
1454 [(set FPR8:$Rt,
1457 [(set (f16 FPR16:$Rt),
1460 [(set (f32 FPR32:$Rt),
1463 [(set (f64 FPR64:$Rt),
1466 [(set (f128 FPR128:$Rt),
1546 [(set GPR32:$Rt,
1550 [(set GPR32:$Rt,
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DAArch64InstrFormats.td841 // System instructions which do not have an Rt register.
848 // System instructions which have an Rt register.
852 bits<5> Rt;
853 let Inst{4-0} = Rt;
933 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
934 "mrs", "\t$Rt, $systemreg"> {
942 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
943 "msr", "\t$systemreg, $Rt"> {
1017 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
1018 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
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/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp838 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeUnsignedLdStInstruction() local
849 Inst.addOperand(MCOperand::createImm(Rt)); in DecodeUnsignedLdStInstruction()
859 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
866 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
870 DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
874 DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
878 DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
882 DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
886 DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder); in DecodeUnsignedLdStInstruction()
899 unsigned Rt = fieldFromInstruction(insn, 0, 5); in DecodeSignedLdStInstruction() local
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/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp565 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeAddiGroupBranch() local
569 if (Rs >= Rt) { in DecodeAddiGroupBranch()
572 } else if (Rs != 0 && Rs < Rt) { in DecodeAddiGroupBranch()
583 Rt))); in DecodeAddiGroupBranch()
604 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeDaddiGroupBranch() local
608 if (Rs >= Rt) { in DecodeDaddiGroupBranch()
611 } else if (Rs != 0 && Rs < Rt) { in DecodeDaddiGroupBranch()
622 Rt))); in DecodeDaddiGroupBranch()
644 InsnType Rt = fieldFromInstruction(insn, 16, 5); in DecodeBlezlGroupBranch() local
648 if (Rt == 0) in DecodeBlezlGroupBranch()
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/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1466 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode2IdxInstruction() local
1491 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1525 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1614 unsigned Rt = fieldFromInstruction(Insn, 12, 4); in DecodeAddrMode3Instruction() local
1623 unsigned Rt2 = Rt + 1; in DecodeAddrMode3Instruction()
1635 if (Rt & 0x1) S = MCDisassembler::SoftFail; in DecodeAddrMode3Instruction()
1647 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1659 if (Rt == 15) in DecodeAddrMode3Instruction()
1661 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
1676 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) in DecodeAddrMode3Instruction()
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/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-thumbv7.txt82 # The unpriviledged Load/Store cannot have SP or PC as Rt.
92 # invalid LDRSHs Rt=PC
97 # invalid LDRSHi8 Rt=PC
102 # invalid LDRSHi12 Rt=PC
113 # if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints"
124 # if Rt = '1111' then SEE "Unallocated memory hints"
236 # Rt == Rn is UNPREDICTABLE
/external/llvm/test/MC/AArch64/
Darm64-diags.s155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
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