| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 43 unsigned Opc = MI->getOpcode(); in isLoadFromStackSlot() local
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
65 unsigned Opc = MI->getOpcode(); in isStoreToStackSlot() local
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || in isStoreToStackSlot()
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { in isStoreToStackSlot()
83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
89 Opc = Mips::MOVE16_MM; in copyPhysReg()
91 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
93 Opc = Mips::CFC1; in copyPhysReg()
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| D | Mips16InstrInfo.cpp | 65 unsigned Opc = 0; in copyPhysReg() local
69 Opc = Mips::MoveR3216; in copyPhysReg()
72 Opc = Mips::Move32R16; in copyPhysReg()
75 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg()
79 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg()
82 assert(Opc && "Cannot copy registers"); in copyPhysReg()
84 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg()
102 unsigned Opc = 0; in storeRegToStack() local
104 Opc = Mips::SwRxSpImmX16; in storeRegToStack()
105 assert(Opc && "Register class not handled!"); in storeRegToStack()
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| D | MipsFastISel.cpp | 149 MachineInstrBuilder emitInst(unsigned Opc) { in emitInst() argument
150 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)); in emitInst()
152 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) { in emitInst() argument
153 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), in emitInst()
156 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg, in emitInstStore() argument
158 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
160 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg, in emitInstLoad() argument
162 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
238 unsigned Opc; in emitLogicalOp() local
241 Opc = Mips::AND; in emitLogicalOp()
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| D | Mips16ISelDAGToDAG.cpp | 47 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty, in selectMULT() argument
50 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0), in selectMULT()
262 unsigned Opc = InFlag.getOpcode(); (void)Opc; in selectNode() local
263 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectNode()
264 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectNode()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandPredSpillCode.cpp | 82 int Opc = MI->getOpcode(); in runOnMachineFunction() local
83 if (Opc == Hexagon::S2_storerb_pci_pseudo || in runOnMachineFunction()
84 Opc == Hexagon::S2_storerh_pci_pseudo || in runOnMachineFunction()
85 Opc == Hexagon::S2_storeri_pci_pseudo || in runOnMachineFunction()
86 Opc == Hexagon::S2_storerd_pci_pseudo || in runOnMachineFunction()
87 Opc == Hexagon::S2_storerf_pci_pseudo) { in runOnMachineFunction()
89 if (Opc == Hexagon::S2_storerd_pci_pseudo) in runOnMachineFunction()
91 else if (Opc == Hexagon::S2_storeri_pci_pseudo) in runOnMachineFunction()
93 else if (Opc == Hexagon::S2_storerh_pci_pseudo) in runOnMachineFunction()
95 else if (Opc == Hexagon::S2_storerf_pci_pseudo) in runOnMachineFunction()
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| D | HexagonCFGOptimizer.cpp | 58 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch() argument
59 return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf) in IsConditionalBranch()
60 || (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt); in IsConditionalBranch()
64 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump() argument
65 return (Opc == Hexagon::J2_jump); in IsUnconditionalJump()
111 int Opc = MI->getOpcode(); in runOnMachineFunction() local
112 if (IsConditionalBranch(Opc)) { in runOnMachineFunction()
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| D | HexagonSplitConst32AndConst64.cpp | 90 int Opc = MI->getOpcode(); in runOnMachineFunction() local
91 if (Opc == Hexagon::CONST32_Int_Real && in runOnMachineFunction()
106 else if (Opc == Hexagon::CONST32_Int_Real || in runOnMachineFunction()
107 Opc == Hexagon::CONST32_Float_Real) { in runOnMachineFunction()
113 if (Opc == Hexagon::CONST32_Float_Real) { in runOnMachineFunction()
125 else if (Opc == Hexagon::CONST64_Int_Real || in runOnMachineFunction()
126 Opc == Hexagon::CONST64_Float_Real) { in runOnMachineFunction()
132 if (Opc == Hexagon::CONST64_Float_Real) { in runOnMachineFunction()
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| D | HexagonGenPredicate.cpp | 94 unsigned getPredForm(unsigned Opc);
96 bool isScalarCmp(unsigned Opc);
120 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm() argument
123 switch (Opc) { in getPredForm()
166 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
167 if (getPredForm(Opc) != 0) in isConvertibleToPredForm()
174 switch (Opc) { in isConvertibleToPredForm()
190 unsigned Opc = MI->getOpcode(); in collectPredicateGPR() local
191 switch (Opc) { in collectPredicateGPR()
238 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
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| D | HexagonBitSimplify.cpp | 179 static bool getUsedBitsInStore(unsigned Opc, BitVector &Bits,
181 static bool getUsedBits(unsigned Opc, unsigned OpN, BitVector &Bits,
428 bool HexagonBitSimplify::getUsedBitsInStore(unsigned Opc, BitVector &Bits, in getUsedBitsInStore() argument
432 switch (Opc) { in getUsedBitsInStore()
588 bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN, in getUsedBits() argument
592 const MCInstrDesc &D = HII.get(Opc); in getUsedBits()
595 return getUsedBitsInStore(Opc, Bits, Begin); in getUsedBits()
599 switch (Opc) { in getUsedBits()
957 unsigned Opc = MI->getOpcode(); in runOnNode() local
960 if (Opc == TargetOpcode::LIFETIME_START || in runOnNode()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelDAGToDAG.cpp | 611 unsigned Opc; in SelectAddrSpaceCast() local
615 Opc = TM.is64Bit() ? NVPTX::cvta_global_yes_64 : NVPTX::cvta_global_yes; in SelectAddrSpaceCast()
618 Opc = TM.is64Bit() ? NVPTX::cvta_shared_yes_64 : NVPTX::cvta_shared_yes; in SelectAddrSpaceCast()
621 Opc = TM.is64Bit() ? NVPTX::cvta_const_yes_64 : NVPTX::cvta_const_yes; in SelectAddrSpaceCast()
624 Opc = TM.is64Bit() ? NVPTX::cvta_local_yes_64 : NVPTX::cvta_local_yes; in SelectAddrSpaceCast()
627 return CurDAG->getMachineNode(Opc, SDLoc(N), N->getValueType(0), Src); in SelectAddrSpaceCast()
632 unsigned Opc; in SelectAddrSpaceCast() local
636 Opc = TM.is64Bit() ? NVPTX::cvta_to_global_yes_64 in SelectAddrSpaceCast()
640 Opc = TM.is64Bit() ? NVPTX::cvta_to_shared_yes_64 in SelectAddrSpaceCast()
644 Opc = in SelectAddrSpaceCast()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 107 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
416 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument
417 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode()
421 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode() argument
422 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; in isCondBranchOpcode()
426 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode() argument
427 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || in isJumpTableBranchOpcode()
428 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; in isJumpTableBranchOpcode()
432 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode() argument
433 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode()
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| D | ARMFastISel.cpp | 474 unsigned Opc; in ARMMaterializeFP() local
477 Opc = ARM::FCONSTD; in ARMMaterializeFP()
480 Opc = ARM::FCONSTS; in ARMMaterializeFP()
484 TII.get(Opc), DestReg).addImm(Imm)); in ARMMaterializeFP()
499 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
503 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg) in ARMMaterializeFP()
518 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
523 TII.get(Opc), ImmReg) in ARMMaterializeInt()
534 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
539 TII.get(Opc), ImmReg) in ARMMaterializeInt()
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| D | ARMISelDAGToDAG.cpp | 114 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
117 SDValue &Offset, SDValue &Opc);
119 SDValue &Opc) { in SelectAddrMode2Base() argument
120 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE; in SelectAddrMode2Base()
124 SDValue &Opc) { in SelectAddrMode2ShOp() argument
125 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP; in SelectAddrMode2ShOp()
129 SDValue &Opc) { in SelectAddrMode2() argument
130 SelectAddrMode2Worker(N, Base, Offset, Opc); in SelectAddrMode2()
144 SDValue &Offset, SDValue &Opc);
146 SDValue &Offset, SDValue &Opc);
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| D | ARMLoadStoreOptimizer.cpp | 349 static bool isT1i32Load(unsigned Opc) { in isT1i32Load() argument
350 return Opc == ARM::tLDRi || Opc == ARM::tLDRspi; in isT1i32Load()
353 static bool isT2i32Load(unsigned Opc) { in isT2i32Load() argument
354 return Opc == ARM::t2LDRi12 || Opc == ARM::t2LDRi8; in isT2i32Load()
357 static bool isi32Load(unsigned Opc) { in isi32Load() argument
358 return Opc == ARM::LDRi12 || isT1i32Load(Opc) || isT2i32Load(Opc) ; in isi32Load()
361 static bool isT1i32Store(unsigned Opc) { in isT1i32Store() argument
362 return Opc == ARM::tSTRi || Opc == ARM::tSTRspi; in isT1i32Store()
365 static bool isT2i32Store(unsigned Opc) { in isT2i32Store() argument
366 return Opc == ARM::t2STRi12 || Opc == ARM::t2STRi8; in isT2i32Store()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
452 unsigned Opc; in PPCEmitLoad() local
476 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8; in PPCEmitLoad()
479 Opc = (IsZExt ? in PPCEmitLoad()
484 Opc = (IsZExt ? in PPCEmitLoad()
487 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0)) in PPCEmitLoad()
491 Opc = PPC::LD; in PPCEmitLoad()
497 Opc = PPC::LFS; in PPCEmitLoad()
500 Opc = FP64LoadOpc; in PPCEmitLoad()
513 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS; in PPCEmitLoad()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 96 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
128 bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc,
351 unsigned Opc = 0; in X86FastEmitLoad() local
357 Opc = X86::MOV8rm; in X86FastEmitLoad()
361 Opc = X86::MOV16rm; in X86FastEmitLoad()
365 Opc = X86::MOV32rm; in X86FastEmitLoad()
370 Opc = X86::MOV64rm; in X86FastEmitLoad()
375 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; in X86FastEmitLoad()
378 Opc = X86::LD_Fp32m; in X86FastEmitLoad()
384 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; in X86FastEmitLoad()
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| D | X86ISelDAGToDAG.cpp | 200 SDNode *selectGather(SDNode *N, unsigned Opc);
1945 unsigned Opc = 0; in selectAtomicLoadArith() local
1950 Opc = AtomicOpcTbl[Op][ConstantI8]; in selectAtomicLoadArith()
1952 Opc = AtomicOpcTbl[Op][I8]; in selectAtomicLoadArith()
1957 Opc = AtomicOpcTbl[Op][SextConstantI16]; in selectAtomicLoadArith()
1959 Opc = AtomicOpcTbl[Op][ConstantI16]; in selectAtomicLoadArith()
1961 Opc = AtomicOpcTbl[Op][I16]; in selectAtomicLoadArith()
1966 Opc = AtomicOpcTbl[Op][SextConstantI32]; in selectAtomicLoadArith()
1968 Opc = AtomicOpcTbl[Op][ConstantI32]; in selectAtomicLoadArith()
1970 Opc = AtomicOpcTbl[Op][I32]; in selectAtomicLoadArith()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ConditionalCompares.cpp | 580 unsigned Opc = 0; in convert() local
584 Opc = AArch64::SUBSWri; in convert()
588 Opc = AArch64::SUBSXri; in convert()
593 const MCInstrDesc &MCID = TII->get(Opc); in convert()
612 unsigned Opc = 0; in convert() local
618 case AArch64::SUBSWri: Opc = AArch64::CCMPWi; break; in convert()
619 case AArch64::SUBSWrr: Opc = AArch64::CCMPWr; break; in convert()
620 case AArch64::SUBSXri: Opc = AArch64::CCMPXi; break; in convert()
621 case AArch64::SUBSXrr: Opc = AArch64::CCMPXr; break; in convert()
622 case AArch64::ADDSWri: Opc = AArch64::CCMNWi; break; in convert()
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| D | AArch64InstrInfo.cpp | 304 unsigned Opc = 0; in canFoldIntoCSel() local
320 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; in canFoldIntoCSel()
330 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; in canFoldIntoCSel()
347 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; in canFoldIntoCSel()
353 assert(Opc && SrcOpNum && "Missing parameters"); in canFoldIntoCSel()
357 return Opc; in canFoldIntoCSel()
485 unsigned Opc = 0; in insertSelect() local
490 Opc = AArch64::CSELXr; in insertSelect()
494 Opc = AArch64::CSELWr; in insertSelect()
498 Opc = AArch64::FCSELDrrr; in insertSelect()
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| D | AArch64ConditionOptimizer.cpp | 199 static int getComplementOpc(int Opc) { in getComplementOpc() argument
200 switch (Opc) { in getComplementOpc()
226 unsigned Opc = CmpMI->getOpcode(); in adjustCmp() local
230 bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri); in adjustCmp()
245 Opc = getComplementOpc(Opc); in adjustCmp()
248 return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp)); in adjustCmp()
255 unsigned Opc; in modifyCmp() local
257 std::tie(Imm, Opc, Cmp) = Info; in modifyCmp()
262 BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc)) in modifyCmp()
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| D | AArch64LoadStoreOptimizer.cpp | 149 static bool isUnscaledLdSt(unsigned Opc) { in isUnscaledLdSt() argument
150 switch (Opc) { in isUnscaledLdSt()
195 static bool isNarrowStore(unsigned Opc) { in isNarrowStore() argument
196 switch (Opc) { in isNarrowStore()
211 static bool isNarrowLoad(unsigned Opc) { in isNarrowLoad() argument
212 switch (Opc) { in isNarrowLoad()
289 static unsigned getMatchingNonSExtOpcode(unsigned Opc, in getMatchingNonSExtOpcode() argument
293 switch (Opc) { in getMatchingNonSExtOpcode()
326 return Opc; in getMatchingNonSExtOpcode()
342 static unsigned getMatchingPairOpcode(unsigned Opc) { in getMatchingPairOpcode() argument
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| D | AArch64FastISel.cpp | 370 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; in materializeFP() local
371 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
403 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui; in materializeFP() local
405 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in materializeFP()
491 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr; in fastMaterializeFloatZero() local
492 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
1259 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rr() local
1268 const MCInstrDesc &II = TII.get(Opc); in emitAddSub_rr()
1301 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_ri() local
1313 const MCInstrDesc &II = TII.get(Opc); in emitAddSub_ri()
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| D | AArch64InstrInfo.h | 241 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } in isUncondBranchOpcode() argument
243 static inline bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode() argument
244 switch (Opc) { in isCondBranchOpcode()
260 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; } in isIndirectBranchOpcode() argument
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SILoadStoreOptimizer.cpp | 227 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64; in mergeRead2Pair() local
235 Opc = (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64; in mergeRead2Pair()
242 const MCInstrDesc &Read2Desc = TII->get(Opc); in mergeRead2Pair()
323 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64; in mergeWrite2Pair() local
331 Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32 : AMDGPU::DS_WRITE2ST64_B64; in mergeWrite2Pair()
338 const MCInstrDesc &Write2Desc = TII->get(Opc); in mergeWrite2Pair()
394 unsigned Opc = MI.getOpcode(); in optimizeBlock() local
395 if (Opc == AMDGPU::DS_READ_B32 || Opc == AMDGPU::DS_READ_B64) { in optimizeBlock()
396 unsigned Size = (Opc == AMDGPU::DS_READ_B64) ? 8 : 4; in optimizeBlock()
406 } else if (Opc == AMDGPU::DS_WRITE_B32 || Opc == AMDGPU::DS_WRITE_B64) { in optimizeBlock()
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| /external/llvm/utils/TableGen/ |
| D | FixedLenDecoderEmitter.cpp | 414 void SingletonExists(unsigned Opc) const;
432 unsigned Opc) const;
434 bool doesOpcodeNeedPredicate(unsigned Opc) const;
437 unsigned Opc) const;
440 unsigned Opc) const;
444 unsigned Opc) const;
454 void emitDecoder(raw_ostream &OS, unsigned Indentation, unsigned Opc,
456 unsigned getDecoderIndex(DecoderSet &Decoders, unsigned Opc,
795 unsigned Opc = decodeULEB128(Buffer); in emitTable() local
809 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n"; in emitTable()
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