/device/linaro/bootloader/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ |
D | div.asm | 34 RSBS r12, r1, r0, LSR #4 37 RSBS r12, r1, r0, LSR #8 52 ORRS r12, r0, r1 54 RSBS r12, r1, r0, LSR #1 57 RSBS r12, r1, r0, LSR #4 59 RSBS r12, r1, r0, LSR #8 64 RSBS r12, r1, r0, LSR #7 65 SUBCS r0, r0, r1, LSL #7 67 RSBS r12, r1, r0,LSR #6 68 SUBCS r0, r0, r1, LSL #6 [all …]
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D | div.S | 35 rsbs r12, r1, r0, LSR #4 38 rsbs r12, r1, r0, LSR #8 53 orrs r12, r0, r1 55 rsbs r12, r1, r0, LSR #1 58 rsbs r12, r1, r0, LSR #4 60 rsbs r12, r1, r0, LSR #8 65 rsbs r12, r1, r0, LSR #7 66 subcs r0, r0, r1, LSL #7 68 rsbs r12, r1, r0,LSR #6 69 subcs r0, r0, r1, LSL #6 [all …]
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D | ctzsi2.S | 20 uxth r3, r0 25 mov r0, r0, lsr ip 26 tst r0, #255 29 mov r0, r0, lsr r3 30 tst r0, #15 34 mov r0, r0, lsr r1 35 tst r0, #3 39 mov r0, r0, lsr r2 40 and r0, r0, #3 42 eor r3, r0, #1 [all …]
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D | clzsi2.S | 23 movs r3, r0, lsr #16 28 mov r3, r0, lsr r3 30 movne r0, #8 31 moveq r0, #0 34 mov r3, r3, lsr r0 36 movne r0, #4 37 moveq r0, #0 40 mov r3, r3, lsr r0 42 movne r0, #2 43 moveq r0, #0 [all …]
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D | udivmoddi4.S | 28 mov r10, r0 40 stmia r6, {r0-r1} 43 mov r0, r10 48 stmiane r6, {r0-r1} 60 mov r0, r11 63 stmia r6, {r0-r1} 66 mov r0, r11 70 mov r10, r0 74 subs r1, r0, #0 79 mov r0, r11 [all …]
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/device/linaro/bootloader/edk2/BeagleBoardPkg/Sec/Arm/ |
D | ModuleEntryPoint.asm | 30 mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register 31 bic r0, r0, #0x00000002 // disable L2 cache 32 mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register 35 mrc p15, 0, r0, c1, c0, 0 36 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 37 bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */ 38 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ 39 orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ 40 mcr p15, 0, r0, c1, c0, 0 43 mrc p15, 0, r0, c1, c0, 2 [all …]
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D | ModuleEntryPoint.S | 27 mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register 28 bic r0, r0, #0x00000002 // disable L2 cache 29 mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register 32 mrc p15, 0, r0, c1, c0, 0 33 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 34 bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */ 35 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ 36 orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ 37 mcr p15, 0, r0, c1, c0, 0 40 mrc p15, 0, r0, c1, c0, 2 [all …]
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/device/linaro/bootloader/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Sec/Arm/ |
D | ModuleEntryPoint.asm | 30 mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register 31 bic r0, r0, #0x00000002 // disable L2 cache 32 mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register 35 mrc p15, 0, r0, c1, c0, 0 36 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 37 bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */ 38 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ 39 orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ 40 mcr p15, 0, r0, c1, c0, 0 43 mrc p15, 0, r0, c1, c0, 2 [all …]
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D | ModuleEntryPoint.S | 27 mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register 28 bic r0, r0, #0x00000002 // disable L2 cache 29 mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register 32 mrc p15, 0, r0, c1, c0, 0 33 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ 34 bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */ 35 orr r0, r0, #0x00000002 /* set bit 1 (A) Align */ 36 orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */ 37 mcr p15, 0, r0, c1, c0, 0 40 mrc p15, 0, r0, c1, c0, 2 [all …]
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/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/ |
D | RTSMHelper.asm | 46 mrc p15, 4, r0, c15, c0, 0 55 LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0) 56 ldr r0, [r0] 70 mov r0, #ARM_CPU_TYPE_MASK 71 and r1, r1, r0 73 mov r0, #ARM_CPU_TYPE_A15 74 cmp r1, r0 81 ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] ; Read SCU Config reg to get CPU count 85 mrc p15, 1, r0, c9, c0, 2 ; Read C9 register of CP15 to get CPU count 86 lsr r0, #24 [all …]
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D | RTSMHelper.S | 39 # OUT r0 = SCU Base Address 44 mrc p15, 4, r0, c15, c0, 0 52 LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0) 53 ldr r0, [r0] 57 # OUT r0 = number of cores present in the system 66 LoadConstantToReg (ARM_CPU_TYPE_MASK, r0) 67 and r1, r1, r0 69 LoadConstantToReg (ARM_CPU_TYPE_A15, r0) 70 cmp r1, r0 77 ldr r0, [r0, #A9_SCU_CONFIG_OFFSET] @ Read SCU Config reg to get CPU count [all …]
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/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ |
D | CTA15-A7Helper.S | 35 and r1, r0, #ARM_CORE_MASK 36 and r0, r0, #ARM_CLUSTER_MASK 37 add r0, r1, r0, LSR #7 62 and r0, r0, r2 65 cmp r0, r1 66 moveq r0, #1 67 movne r0, #0 77 LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r0) 78 ldr r0, [r0] 79 lsr r0, #24 [all …]
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D | CTA15-A7Helper.asm | 38 and r1, r0, #ARM_CORE_MASK 39 and r0, r0, #ARM_CLUSTER_MASK 40 add r0, r1, r0, LSR #7 66 and r0, r0, r2 69 cmp r0, r1 70 moveq r0, #1 71 movne r0, #0 82 LoadConstantToReg (ARM_CTA15A7_SCC_CFGREG48, r0) 83 ldr r0, [r0] 84 lsr r0, #24 [all …]
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/device/linaro/bootloader/edk2/ArmPkg/Include/ |
D | AsmMacroIoLib.h | 30 ldr r0, [pc, #8] ; \ 31 str r0, [r1] ; \ 41 ldr r0, [r1] ; \ 42 orr r0, r0, r2 ; \ 43 str r0, [r1] ; \ 53 ldr r0, [r1] ; \ 54 and r0, r0, r2 ; \ 55 str r0, [r1] ; \ 64 ldr r0, [r1] ; \ 66 and r0, r0, r2 ; \ [all …]
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/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/Arm/ |
D | ArmJunoHelper.S | 45 and r1, r0, #ARM_CORE_MASK 46 and r0, r0, #ARM_CLUSTER_MASK 47 add r0, r1, r0, LSR #7 63 ldr r0, =PrimaryCoreMpid 64 ldr r0, [r0] 83 and r0, r0, r1 88 cmp r0, r1 89 moveq r0, #1 90 movne r0, #0 104 str r0, [r1]
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/device/linaro/bootloader/edk2/ArmPlatformPkg/Library/ArmPlatformLibNull/Arm/ |
D | ArmPlatformHelper.S | 36 and r1, r0, #ARM_CORE_MASK 37 and r0, r0, #ARM_CLUSTER_MASK 38 add r0, r1, r0, LSR #7 46 LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0) 47 ldr r0, [r0] 57 and r0, r0, r1 60 cmp r0, r1 61 moveq r0, #1 62 movne r0, #0
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D | ArmPlatformHelper.asm | 39 and r1, r0, #ARM_CORE_MASK 40 and r0, r0, #ARM_CLUSTER_MASK 41 add r0, r1, r0, LSR #7 50 LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r0) 51 ldr r0, [r0] 62 and r0, r0, r1 65 cmp r0, r1 66 moveq r0, #1 67 movne r0, #0
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmHvcLib/Arm/ |
D | ArmHvc.asm | 21 push {r0} 24 ldr r7, [r0, #28] 25 ldr r6, [r0, #24] 26 ldr r5, [r0, #20] 27 ldr r4, [r0, #16] 28 ldr r3, [r0, #12] 29 ldr r2, [r0, #8] 30 ldr r1, [r0, #4] 31 ldr r0, [r0, #0] 43 str r0, [r8, #0] [all …]
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D | ArmHvc.S | 24 push {r0} 27 ldr r7, [r0, #28] 28 ldr r6, [r0, #24] 29 ldr r5, [r0, #20] 30 ldr r4, [r0, #16] 31 ldr r3, [r0, #12] 32 ldr r2, [r0, #8] 33 ldr r1, [r0, #4] 34 ldr r0, [r0, #0] 46 str r0, [r8, #0] [all …]
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmSmcLib/Arm/ |
D | ArmSmc.asm | 20 push {r0} 23 ldr r7, [r0, #28] 24 ldr r6, [r0, #24] 25 ldr r5, [r0, #20] 26 ldr r4, [r0, #16] 27 ldr r3, [r0, #12] 28 ldr r2, [r0, #8] 29 ldr r1, [r0, #4] 30 ldr r0, [r0, #0] 42 str r0, [r8, #0] [all …]
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D | ArmSmc.S | 23 push {r0} 26 ldr r7, [r0, #28] 27 ldr r6, [r0, #24] 28 ldr r5, [r0, #20] 29 ldr r4, [r0, #16] 30 ldr r3, [r0, #12] 31 ldr r2, [r0, #8] 32 ldr r1, [r0, #4] 33 ldr r0, [r0, #0] 45 str r0, [r8, #0] [all …]
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/device/google/contexthub/firmware/lib/libc/ |
D | memcpy-armv7m.S | 90 @ r0: dst 96 mov ip, r0 98 push {r0} 100 orr r3, r1, r0 114 str r3, [r0], #4 118 str r3, [r0, \offset] 120 adds r0, __OPT_BIG_BLOCK_SIZE 136 str r3, [r0], #4 140 str r3, [r0, \offset] 142 adds r0, __OPT_MID_BLOCK_SIZE [all …]
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/device/linaro/bootloader/edk2/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibCTA9x4/ |
D | CTA9x4Boot.S | 102 ldr r0, [r2, #0] 103 ldr r0, [r2, #0] 104 ldr r0, = 0x00000000 105 str r0, [r2, #0] 106 ldr r0, [r2, #0] 109 ldr r0, [r2, #0] 110 ldr r0, [r2, #0] 111 ldr r0, = 0x00000000 112 str r0, [r2, #0] 113 LoadConstantToReg (0x00900090, r0) [all …]
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Common/Arm/ |
D | ArmLibSupport.asm | 46 mcr p15,0,r0,c3,c0,0 53 bic r2, r2, r0 // clear mask in the cpsr 54 and r1, r1, r0 // clear bits outside the mask in the input 63 mrs r0, cpsr 67 mrc p15, 0, r0, c1, c0, 2 71 mcr p15, 0, r0, c1, c0, 2 76 mcr p15, 0, r0, c1, c0, 1 80 mrc p15, 0, r0, c1, c0, 1 84 mcr p15,0,r0,c2,c0,0 89 mrc p15,0,r0,c2,c0,0 [all …]
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/device/linaro/hikey/l-loader/ |
D | start.S | 42 str r0, [r8] @ download mode (1:usb,2:uart,0:boot) 51 ldr r0, [r4, r5] 52 cmp r0, r6 58 ldr r0, [r4, r5] @ Load ACPU_SC_CPUx_CTRL 59 orr r0, r0, #CPU_CTRL_AARCH64_MODE 60 str r0, [r4, r5] @ Save to ACPU_SC_CPUx_CTRL 61 ldr r0, [r4, r5] 72 mov r0, #0 73 str r0, [r4] 74 str r0, [r4, #4] @ UART2_TXD IOMG register [all …]
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