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Searched refs:VT (Results 1 – 25 of 222) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp947 EVT VT = N->getValueType(0); in SelectTable() local
962 return CurDAG->getMachineNode(Opc, dl, VT, Ops); in SelectTable()
969 EVT VT = LD->getMemoryVT(); in SelectIndexedLoad() local
981 if (VT == MVT::i64) in SelectIndexedLoad()
983 else if (VT == MVT::i32) { in SelectIndexedLoad()
995 } else if (VT == MVT::i16) { in SelectIndexedLoad()
1008 } else if (VT == MVT::i8) { in SelectIndexedLoad()
1021 } else if (VT == MVT::f32) { in SelectIndexedLoad()
1023 } else if (VT == MVT::f64 || VT.is64BitVector()) { in SelectIndexedLoad()
1025 } else if (VT.is128BitVector()) { in SelectIndexedLoad()
[all …]
DAArch64ISelLowering.cpp429 for (MVT VT : MVT::fp_valuetypes()) { in AArch64TargetLowering() local
430 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); in AArch64TargetLowering()
431 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); in AArch64TargetLowering()
432 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); in AArch64TargetLowering()
433 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand); in AArch64TargetLowering()
435 for (MVT VT : MVT::integer_valuetypes()) in AArch64TargetLowering() local
436 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Expand); in AArch64TargetLowering()
587 for (MVT VT : MVT::vector_valuetypes()) { in AArch64TargetLowering() local
588 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand); in AArch64TargetLowering()
590 setOperationAction(ISD::MULHS, VT, Expand); in AArch64TargetLowering()
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.cpp106 EVT VT = Op.getValueType(); in LowerINTRINSIC_WO_CHAIN() local
113 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
115 return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
119 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
121 return DAG.getNode(AMDGPUISD::MAD, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
124 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
127 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
130 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
133 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1), in LowerINTRINSIC_WO_CHAIN()
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DR600ISelLowering.cpp277 EVT VT = Op.getValueType(); in LowerOperation() local
284 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT); in LowerOperation()
288 return LowerImplicitParameter(DAG, VT, DL, 0); in LowerOperation()
290 return LowerImplicitParameter(DAG, VT, DL, 1); in LowerOperation()
292 return LowerImplicitParameter(DAG, VT, DL, 2); in LowerOperation()
294 return LowerImplicitParameter(DAG, VT, DL, 3); in LowerOperation()
296 return LowerImplicitParameter(DAG, VT, DL, 4); in LowerOperation()
298 return LowerImplicitParameter(DAG, VT, DL, 5); in LowerOperation()
300 return LowerImplicitParameter(DAG, VT, DL, 6); in LowerOperation()
302 return LowerImplicitParameter(DAG, VT, DL, 7); in LowerOperation()
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DAMDILISelLowering.cpp106 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x]; in InitAMDILLowering() local
110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); in InitAMDILLowering()
111 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
112 setOperationAction(ISD::SUBC, VT, Expand); in InitAMDILLowering()
113 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
114 setOperationAction(ISD::ADDC, VT, Expand); in InitAMDILLowering()
115 setOperationAction(ISD::BRCOND, VT, Custom); in InitAMDILLowering()
116 setOperationAction(ISD::BR_JT, VT, Expand); in InitAMDILLowering()
117 setOperationAction(ISD::BRIND, VT, Expand); in InitAMDILLowering()
119 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
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/external/llvm/include/llvm/Target/
DTargetLowering.h203 getPreferredVectorAction(EVT VT) const { in getPreferredVectorAction() argument
205 if (VT.getVectorNumElements() == 1) in getPreferredVectorAction()
314 virtual bool enableAggressiveFMAFusion(EVT VT) const { in enableAggressiveFMAFusion() argument
319 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
364 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor() argument
365 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; in getRegClassFor()
377 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const { in getRepRegClassFor() argument
378 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy]; in getRepRegClassFor()
384 virtual uint8_t getRepRegClassCostFor(MVT VT) const { in getRepRegClassCostFor() argument
385 return RepRegClassCostForVT[VT.SimpleTy]; in getRepRegClassCostFor()
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/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType() argument
88 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentMemType()
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) { in getEquivalentLoadRegType() argument
98 unsigned StoreSize = VT.getStoreSizeInBits(); in getEquivalentLoadRegType()
221 for (MVT VT : MVT::integer_valuetypes()) { in AMDGPUTargetLowering() local
222 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
223 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand); in AMDGPUTargetLowering()
227 for (MVT VT : MVT::integer_vector_valuetypes()) { in AMDGPUTargetLowering() local
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand); in AMDGPUTargetLowering()
[all …]
DSIISelLowering.cpp130 for (MVT VT : MVT::integer_valuetypes()) { in SITargetLowering() local
131 if (VT == MVT::i64) in SITargetLowering()
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
136 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
137 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in SITargetLowering()
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal); in SITargetLowering()
141 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal); in SITargetLowering()
142 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand); in SITargetLowering()
[all …]
DR600ISelLowering.cpp125 for (MVT VT : MVT::integer_valuetypes()) { in R600TargetLowering() local
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
127 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
128 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
130 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
131 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
134 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in R600TargetLowering()
135 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Custom); in R600TargetLowering()
136 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Custom); in R600TargetLowering()
[all …]
/external/llvm/lib/Target/X86/Utils/
DX86ShuffleDecode.h39 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
41 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
43 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
45 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
47 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
49 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
51 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
53 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
60 void DecodeSHUFPMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
65 void DecodeUNPCKHMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
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DX86ShuffleDecode.cpp66 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSLDUPMask() argument
67 unsigned NumElts = VT.getVectorNumElements(); in DecodeMOVSLDUPMask()
74 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVSHDUPMask() argument
75 unsigned NumElts = VT.getVectorNumElements(); in DecodeMOVSHDUPMask()
82 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask) { in DecodeMOVDDUPMask() argument
83 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodeMOVDDUPMask()
84 unsigned ScalarSizeInBits = VT.getScalarSizeInBits(); in DecodeMOVDDUPMask()
85 unsigned NumElts = VT.getVectorNumElements(); in DecodeMOVDDUPMask()
96 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask) { in DecodePSLLDQMask() argument
97 unsigned VectorSizeInBits = VT.getSizeInBits(); in DecodePSLLDQMask()
[all …]
/external/llvm/lib/CodeGen/
DCallingConvLower.cpp74 MVT ArgVT = Ins[i].VT; in AnalyzeFormalArguments()
92 MVT VT = Outs[i].VT; in CheckReturn() local
94 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) in CheckReturn()
106 MVT VT = Outs[i].VT; in AnalyzeReturn() local
108 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { in AnalyzeReturn()
111 << EVT(VT).getEVTString() << '\n'; in AnalyzeReturn()
124 MVT ArgVT = Outs[i].VT; in AnalyzeCallOperands()
160 MVT VT = Ins[i].VT; in AnalyzeCallResult() local
162 if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { in AnalyzeCallResult()
165 << EVT(VT).getEVTString() << '\n'; in AnalyzeCallResult()
[all …]
DTargetLoweringBase.cpp667 RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) { in getATOMIC() argument
670 switch (VT.SimpleTy) { \ in getATOMIC()
789 for (MVT VT : MVT::all_valuetypes()) { in initActions() local
793 setIndexedLoadAction(IM, VT, Expand); in initActions()
794 setIndexedStoreAction(IM, VT, Expand); in initActions()
798 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); in initActions()
801 setOperationAction(ISD::FGETSIGN, VT, Expand); in initActions()
802 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
803 setOperationAction(ISD::FMINNUM, VT, Expand); in initActions()
804 setOperationAction(ISD::FMAXNUM, VT, Expand); in initActions()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAG.cpp78 bool ConstantFPSDNode::isValueValidForType(EVT VT, in isValueValidForType() argument
80 assert(VT.isFloatingPoint() && "Can only convert between FP types"); in isValueValidForType()
85 (void) Val2.convert(SelectionDAG::EVTToAPFloatSemantics(VT), in isValueValidForType()
737 EVT VT = N->getValueType(0); in VerifySDNode() local
739 assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && in VerifySDNode()
744 assert(N->getOperand(0).getValueType().isInteger() == VT.isInteger() && in VerifySDNode()
746 assert(VT.getSizeInBits() == 2 * N->getOperand(0).getValueSizeInBits() && in VerifySDNode()
806 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps() local
807 if (VT.isExtended()) { in RemoveNodeFromCSEMaps()
808 Erased = ExtendedValueTypeNodes.erase(VT); in RemoveNodeFromCSEMaps()
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DDAGCombiner.cpp323 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
332 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
431 bool isTypeLegal(const EVT &VT) { in isTypeLegal() argument
433 return TLI.isTypeLegal(VT); in isTypeLegal()
437 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
438 return TLI.getSetCCResultType(*DAG.getContext(), VT); in getSetCCResultType()
769 EVT VT = N0.getValueType(); in ReassociateOps() local
774 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, L, R)) in ReassociateOps()
775 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); in ReassociateOps()
781 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1); in ReassociateOps()
[all …]
DTargetLowering.cpp120 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, in softenSetCCOperands() argument
124 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128) in softenSetCCOperands()
132 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : in softenSetCCOperands()
133 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128; in softenSetCCOperands()
137 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : in softenSetCCOperands()
138 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128; in softenSetCCOperands()
142 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : in softenSetCCOperands()
143 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128; in softenSetCCOperands()
147 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : in softenSetCCOperands()
148 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128; in softenSetCCOperands()
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DLegalizeVectorOps.cpp385 MVT VT = Op.getSimpleValueType(); in Promote() local
388 MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); in Promote()
407 if ((VT.isFloatingPoint() && NVT.isFloatingPoint()) || in Promote()
408 (VT.isVector() && VT.getVectorElementType().isFloatingPoint() && in Promote()
410 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0)); in Promote()
412 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in Promote()
418 EVT VT = Op.getOperand(0).getValueType(); in PromoteINT_TO_FP() local
430 EVT NVT = VT.widenIntegerVectorElementType(*DAG.getContext()); in PromoteINT_TO_FP()
454 EVT VT = Op.getValueType(); in PromoteFP_TO_INT() local
459 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext()); in PromoteFP_TO_INT()
[all …]
DLegalizeDAG.cpp67 EVT getSetCCResultType(EVT VT) const { in getSetCCResultType()
68 return TLI.getSetCCResultType(*DAG.getContext(), VT); in getSetCCResultType()
102 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
106 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl, in ShuffleWithNarrowerEltType() argument
211 unsigned NumMaskElts = VT.getVectorNumElements(); in ShuffleWithNarrowerEltType()
248 EVT VT = CFP->getValueType(0); in ExpandConstantFP() local
251 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); in ExpandConstantFP()
253 (VT == MVT::f64) ? MVT::i64 : MVT::i32); in ExpandConstantFP()
256 EVT OrigVT = VT; in ExpandConstantFP()
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/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h56 SDVTListNode(const FoldingSetNodeIDRef ID, const EVT *VT, unsigned int Num) :
57 FastID(ID), VTs(VT), NumVTs(Num) {
407 SDVTList getVTList(EVT VT);
416 SDValue getConstant(uint64_t Val, EVT VT, bool isTarget = false,
418 SDValue getConstant(const APInt &Val, EVT VT, bool isTarget = false,
420 SDValue getConstant(const ConstantInt &Val, EVT VT, bool isTarget = false,
423 SDValue getTargetConstant(uint64_t Val, EVT VT, bool isOpaque = false) {
424 return getConstant(Val, VT, true, isOpaque);
426 SDValue getTargetConstant(const APInt &Val, EVT VT, bool isOpaque = false) {
427 return getConstant(Val, VT, true, isOpaque);
[all …]
DValueTypes.h41 bool operator==(EVT VT) const {
42 return !(*this != VT);
44 bool operator!=(EVT VT) const {
45 if (V.SimpleTy != VT.V.SimpleTy)
48 return LLVMTy != VT.LLVMTy;
70 static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements) { in getVectorVT()
71 MVT M = MVT::getVectorVT(VT.V, NumElements); in getVectorVT()
74 return getExtendedVectorVT(Context, VT, NumElements); in getVectorVT()
171 bool bitsEq(EVT VT) const { in bitsEq()
172 if (EVT::operator==(VT)) return true; in bitsEq()
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/external/clang/test/SemaCXX/
Dcxx11-call-to-deleted-constructor.cpp10 template <class VT, unsigned int ROWS = 0, unsigned int COLS = 0>
14 typedef VT value_type;
18 template <class VT, unsigned int SIZE> using Vector = Matrix<VT, SIZE, 1>;
20 template <class VT>
21 using RGBValue = Vector<VT, 3>;
24 template <class VT> class Matrix<VT, 0, 0> { // expected-note {{passing argument to parameter here}}
26 typedef VT value_type;
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp77 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
156 for (MVT VT : MVT::integer_valuetypes()) in X86TargetLowering() local
157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
284 MVT VT = IntVTs[i]; in X86TargetLowering() local
285 setOperationAction(ISD::MULHS, VT, Expand); in X86TargetLowering()
286 setOperationAction(ISD::MULHU, VT, Expand); in X86TargetLowering()
287 setOperationAction(ISD::SDIV, VT, Expand); in X86TargetLowering()
288 setOperationAction(ISD::UDIV, VT, Expand); in X86TargetLowering()
289 setOperationAction(ISD::SREM, VT, Expand); in X86TargetLowering()
290 setOperationAction(ISD::UREM, VT, Expand); in X86TargetLowering()
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp628 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT, in getIndexedAddressParts() argument
635 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { in getIndexedAddressParts()
672 EVT VT; in getPostIndexedAddressParts() local
677 VT = LD->getMemoryVT(); in getPostIndexedAddressParts()
680 VT = ST->getMemoryVT(); in getPostIndexedAddressParts()
689 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, in getPostIndexedAddressParts()
692 int ShiftAmount = VT.getSizeInBits() / 16; in getPostIndexedAddressParts()
961 static SDValue createSplat(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue Val) { in createSplat() argument
962 if (VT.getSimpleVT() == MVT::v4i8) in createSplat()
963 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val); in createSplat()
[all …]
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, in addTypeForNEON() argument
95 if (VT != PromotedLdStVT) { in addTypeForNEON()
96 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
99 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
103 MVT ElemTy = VT.getVectorElementType(); in addTypeForNEON()
105 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
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/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp145 bool isTypeLegal(Type *Ty, MVT &VT);
146 bool isLoadTypeLegal(Type *Ty, MVT &VT);
152 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
155 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
157 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
161 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
162 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
163 unsigned PPCMaterializeInt(const Constant *C, MVT VT, bool UseSExt = true);
168 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
170 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
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