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Searched refs:SDValue (Results 1 – 25 of 117) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.h100 SmallDenseMap<SDValue, SDValue, 8> PromotedIntegers;
104 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedIntegers;
108 SmallDenseMap<SDValue, SDValue, 8> SoftenedFloats;
113 SmallDenseMap<SDValue, SDValue, 8> PromotedFloats;
117 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedFloats;
121 SmallDenseMap<SDValue, SDValue, 8> ScalarizedVectors;
125 SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> SplitVectors;
129 SmallDenseMap<SDValue, SDValue, 8> WidenedVectors;
133 SmallDenseMap<SDValue, SDValue, 8> ReplacedValues;
157 ReplacedValues[SDValue(Old, i)] = SDValue(New, i); in NoteDeletion()
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/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.h33 unsigned getMSACtrlReg(const SDValue RegIdx) const;
40 SDNode *selectAddESubE(unsigned MOp, SDValue InFlag, SDValue CmpLHS,
43 bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
44 bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
47 bool selectAddrRegImm(SDValue Addr, SDValue &Base,
48 SDValue &Offset) const override;
50 bool selectAddrRegReg(SDValue Addr, SDValue &Base,
51 SDValue &Offset) const override;
53 bool selectAddrDefault(SDValue Addr, SDValue &Base,
54 SDValue &Offset) const override;
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DMipsISelDAGToDAG.h57 virtual bool selectAddrRegImm(SDValue Addr, SDValue &Base,
58 SDValue &Offset) const;
62 virtual bool selectAddrRegReg(SDValue Addr, SDValue &Base,
63 SDValue &Offset) const;
66 virtual bool selectAddrDefault(SDValue Addr, SDValue &Base,
67 SDValue &Offset) const;
70 virtual bool selectIntAddr(SDValue Addr, SDValue &Base,
71 SDValue &Offset) const;
73 virtual bool selectIntAddrMM(SDValue Addr, SDValue &Base,
74 SDValue &Offset) const;
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DMipsISelDAGToDAG.cpp69 bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base, in selectAddrRegImm()
70 SDValue &Offset) const { in selectAddrRegImm()
75 bool MipsDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base, in selectAddrRegReg()
76 SDValue &Offset) const { in selectAddrRegReg()
81 bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base, in selectAddrDefault()
82 SDValue &Offset) const { in selectAddrDefault()
87 bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base, in selectIntAddr()
88 SDValue &Offset) const { in selectIntAddr()
93 bool MipsDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base, in selectIntAddrMM()
94 SDValue &Offset) const { in selectIntAddrMM()
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DMipsISelLowering.h242 SmallVectorImpl<SDValue> &Results,
246 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
251 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
262 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
296 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
303 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, in getAddrLocal()
306 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrLocal()
308 SDValue Load = in getAddrLocal()
313 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal()
323 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, in getAddrGlobal()
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/external/llvm/include/llvm/CodeGen/
DSelectionDAG.h191 SDValue Root;
336 const SDValue &getRoot() const { return Root; }
339 SDValue getEntryNode() const {
340 return SDValue(const_cast<SDNode *>(&EntryNode), 0);
345 const SDValue &setRoot(SDValue N) {
430 SDValue getConstant(uint64_t Val, SDLoc DL, EVT VT, bool isTarget = false,
432 SDValue getConstant(const APInt &Val, SDLoc DL, EVT VT, bool isTarget = false,
434 SDValue getConstant(const ConstantInt &Val, SDLoc DL, EVT VT,
436 SDValue getIntPtrConstant(uint64_t Val, SDLoc DL, bool isTarget = false);
437 SDValue getTargetConstant(uint64_t Val, SDLoc DL, EVT VT,
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/external/llvm/include/llvm/Target/
DTargetSelectionDAGInfo.h48 virtual SDValue
50 SDValue Chain, in EmitTargetCodeForMemcpy()
51 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemcpy()
52 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemcpy()
56 return SDValue(); in EmitTargetCodeForMemcpy()
65 virtual SDValue
67 SDValue Chain, in EmitTargetCodeForMemmove()
68 SDValue Op1, SDValue Op2, in EmitTargetCodeForMemmove()
69 SDValue Op3, unsigned Align, bool isVolatile, in EmitTargetCodeForMemmove()
72 return SDValue(); in EmitTargetCodeForMemmove()
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/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.h413 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
457 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
458 SDValue &Offset,
465 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
472 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
477 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
484 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
489 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
492 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
493 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
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/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.h32 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33 const SDValue &InitPtr,
34 SDValue Chain,
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
46 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
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DR600ISelLowering.h29 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
30 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
32 SmallVectorImpl<SDValue> &Results,
34 SDValue LowerFormalArguments(
35 SDValue Chain,
40 SmallVectorImpl<SDValue> &InVals) const override;
50 SDValue LowerImplicitParameter(SelectionDAG &DAG, EVT VT,
55 SDValue OptimizeSwizzle(SDValue BuildVector, SDValue Swz[], SelectionDAG &DAG,
57 SDValue vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const;
59 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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DAMDGPUISelDAGToDAG.cpp57 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
59 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
60 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
63 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
64 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
65 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
88 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
89 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
90 SDValue& Offset);
91 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
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DSIISelLowering.h24 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, SDLoc DL,
25 SDValue Chain, unsigned Offset, bool Signed) const;
26 SDValue LowerSampleIntrinsic(unsigned Opcode, const SDValue &Op,
28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
31 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
34 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/XCore/
DXCoreISelLowering.h100 bool isZExtFree(SDValue Val, EVT VT2) const override;
109 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
114 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
147 SDValue LowerCCCArguments(SDValue Chain,
152 SmallVectorImpl<SDValue> &InVals) const;
153 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
157 const SmallVectorImpl<SDValue> &OutVals,
160 SmallVectorImpl<SDValue> &InVals) const;
161 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
162 SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
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/external/llvm/lib/Target/ARM/
DARMISelLowering.h234 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
239 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
260 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
261 SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
262 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
280 bool isZExtFree(SDValue Val, EVT VT2) const override;
282 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
308 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
315 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
316 SDValue &Offset, ISD::MemIndexedMode &AM,
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h231 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
244 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
248 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
273 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
292 bool isZExtFree(SDValue Val, EVT VT2) const override;
408 SDValue
409 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
412 SmallVectorImpl<SDValue> &InVals) const override;
414 SDValue LowerCall(CallLoweringInfo & /*CLI*/,
415 SmallVectorImpl<SDValue> &InVals) const override;
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/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.h27 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
28 SDValue Dst, SDValue Src,
29 SDValue Size, unsigned Align,
34 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc DL,
35 SDValue Chain, SDValue Dst, SDValue Byte,
36 SDValue Size, unsigned Align, bool IsVolatile,
39 std::pair<SDValue, SDValue>
40 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain,
41 SDValue Src1, SDValue Src2, SDValue Size,
45 std::pair<SDValue, SDValue>
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DSystemZISelLowering.h389 void LowerAsmOperandForConstraint(SDValue Op,
391 std::vector<SDValue> &Ops,
429 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
432 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
436 SmallVectorImpl<SDValue> &InVals) const override;
437 SDValue LowerCall(CallLoweringInfo &CLI,
438 SmallVectorImpl<SDValue> &InVals) const override;
444 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
446 const SmallVectorImpl<SDValue> &OutVals,
448 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
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DSystemZSelectionDAGInfo.cpp26 static SDValue emitMemMem(SelectionDAG &DAG, SDLoc DL, unsigned Sequence, in emitMemMem()
27 unsigned Loop, SDValue Chain, SDValue Dst, in emitMemMem()
28 SDValue Src, uint64_t Size) { in emitMemMem()
49 SDValue SystemZSelectionDAGInfo::
50 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in EmitTargetCodeForMemcpy()
51 SDValue Dst, SDValue Src, SDValue Size, unsigned Align, in EmitTargetCodeForMemcpy()
56 return SDValue(); in EmitTargetCodeForMemcpy()
61 return SDValue(); in EmitTargetCodeForMemcpy()
67 static SDValue memsetStore(SelectionDAG &DAG, SDLoc DL, SDValue Chain, in memsetStore()
68 SDValue Dst, uint64_t ByteVal, uint64_t Size, in memsetStore()
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DSystemZISelDAGToDAG.cpp58 SDValue Base;
60 SDValue Index;
118 RxSBGOperands(unsigned Op, SDValue N) in RxSBGOperands()
126 SDValue Input;
136 inline SDValue getImm(const SDNode *Node, uint64_t Imm) const { in getImm()
153 bool selectAddress(SDValue N, SystemZAddressingMode &AM) const;
157 SDValue &Base, SDValue &Disp) const;
159 SDValue &Base, SDValue &Disp, SDValue &Index) const;
164 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
165 SDValue &Base, SDValue &Disp) const;
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUISelLowering.h27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
35 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
38 bool isHWTrueValue(SDValue Op) const;
39 bool isHWFalseValue(SDValue Op) const;
44 virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
48 SmallVectorImpl<SDValue> &InVals) const;
50 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
53 const SmallVectorImpl<SDValue> &OutVals,
56 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/X86/
DX86ISelLowering.h596 bool isZeroNode(SDValue Elt);
640 SDValue getPICJumpTableRelocBase(SDValue Table,
683 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
688 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
692 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
704 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
724 void computeKnownBitsForTargetNode(const SDValue Op,
731 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
738 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
755 void LowerAsmOperandForConstraint(SDValue Op,
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/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.h80 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
86 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h108 bool IsEligibleForTailCallOptimization(SDValue Callee,
111 const SmallVectorImpl<SDValue> &OutVals,
123 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
125 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerEXTRACT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerINSERT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerEH_LABEL(SDValue Op, SelectionDAG &DAG) const;
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DHexagonISelDAGToDAG.cpp78 inline bool SelectAddrGA(SDValue &N, SDValue &R);
79 inline bool SelectAddrGP(SDValue &N, SDValue &R);
80 bool SelectGlobalAddress(SDValue &N, SDValue &R, bool UseGP);
81 bool SelectAddrFI(SDValue &N, SDValue &R);
90 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
92 std::vector<SDValue> &OutOps) override;
116 SDValue XformMskToBitPosU5Imm(uint32_t Imm, SDLoc DL) { in XformMskToBitPosU5Imm()
126 SDValue XformMskToBitPosU4Imm(uint16_t Imm, SDLoc DL) { in XformMskToBitPosU4Imm()
132 SDValue XformMskToBitPosU3Imm(uint8_t Imm, SDLoc DL) { in XformMskToBitPosU3Imm()
145 inline SDValue XformM5ToU5Imm(signed Imm, SDLoc DL) { in XformM5ToU5Imm()
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/external/llvm/lib/Target/Sparc/
DSparcISelLowering.h58 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
63 void computeKnownBitsForTargetNode(const SDValue Op,
79 void LowerAsmOperandForConstraint(SDValue Op,
81 std::vector<SDValue> &Ops,
110 SDValue
111 LowerFormalArguments(SDValue Chain,
116 SmallVectorImpl<SDValue> &InVals) const override;
117 SDValue LowerFormalArguments_32(SDValue Chain,
122 SmallVectorImpl<SDValue> &InVals) const;
123 SDValue LowerFormalArguments_64(SDValue Chain,
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