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Searched refs:Rd (Results 1 – 25 of 75) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonIsetDx.td95 (outs IntRegs:$Rd),
97 "if (p0.new) $Rd = #0"> {
98 bits<4> Rd;
102 let Inst{3-0} = Rd;
108 (outs IntRegs:$Rd),
110 "$Rd = memuh($Rs + #$u3_1)"> {
111 bits<4> Rd;
116 let Inst{3-0} = Rd;
150 (outs IntRegs:$Rd),
152 "$Rd = memub($Rs + #$u4_0)"> {
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DHexagonInstrAlias.td95 // Alias of: $Rd = memXX($Rs+#XX) to $Rd = memXX($Rs)
96 def : InstAlias<"$Rd = memb($Rs)",
97 (L2_loadrb_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
99 def : InstAlias<"$Rd = memub($Rs)",
100 (L2_loadrub_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
102 def : InstAlias<"$Rd = memh($Rs)",
103 (L2_loadrh_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
105 def : InstAlias<"$Rd = memuh($Rs)",
106 (L2_loadruh_io IntRegs:$Rd, IntRegs:$Rs, 0), 0>;
108 def : InstAlias<"$Rd = memw($Rs)",
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DHexagonRegisterInfo.td44 // Rd - 64-bit registers.
45 class Rd<bits<5> num, string n, list<Register> subregs> :
97 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
98 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
99 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
100 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
101 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
102 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
103 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
104 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
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DHexagonInstrInfoV5.td41 // Rd=vaddhub(Rss,Rtt):sat
127 def S5_popcountp : ALU64_rr<(outs IntRegs:$Rd), (ins DoubleRegs:$Rss),
128 "$Rd = popcount($Rss)",
129 [(set I32:$Rd, (HexagonPOPCOUNT I64:$Rss))], "", S_2op_tc_2_SLOT23>,
131 bits<5> Rd;
138 let Inst{4-0} = Rd;
152 : MInst<(outs IntRegs:$Rd),
154 "$Rd = "#mnemonic#"($Rs, $Rt)", [],
157 bits<5> Rd;
169 let Inst{4-0} = Rd;
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DHexagonInstrInfo.td121 : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
122 "$Rd = "#mnemonic#"($Rs, $Rt)",
130 bits<5> Rd;
138 let Inst{4-0} = Rd;
144 : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),
146 "$Rd = "#mnemonic#"($Rs, $Rt)",
157 bits<5> Rd;
168 let Inst{4-0} = Rd;
174 let AsmString = "$Rd = combine($Rs"#Op1#", $Rt"#Op2#")";
185 let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
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DHexagonInstrInfoV3.td102 def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
103 (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
104 [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
111 : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
112 "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
114 bits<5> Rd;
127 let Inst{4-0} = Rd;
260 : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
261 "$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">;
DHexagonInstrInfoV4.td131 let AsmString = "$Rd = "#mnemonic#"($Rs, ~$Rt)";
245 : ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
246 "$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
256 bits<5> Rd;
267 let Inst{4-0} = Rd;
1770 def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
1771 "$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
1772 bits<5> Rd;
1778 let Inst{4-0} = Rd;
1876 def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
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DHexagonFrameLowering.cpp1353 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); in expandAlloca() local
1356 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_sub), Rd) in expandAlloca()
1359 if (Rs != Rd) { in expandAlloca()
1367 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_andir), Rd) in expandAlloca()
1368 .addReg(Rd) in expandAlloca()
1370 if (Rs != Rd) in expandAlloca()
1375 if (Rs == Rd) { in expandAlloca()
1378 .addReg(Rd); in expandAlloca()
1382 BuildMI(MB, AI, DL, HII.get(Hexagon::A2_addi), Rd) in expandAlloca()
1383 .addReg(Rd) in expandAlloca()
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-add.ll9 %Rd = add i32 %lhs, 255
10 ret i32 %Rd
19 %Rd = add i32 %lhs, 256
20 ret i32 %Rd
29 %Rd = add i32 %lhs, 257
30 ret i32 %Rd
39 %Rd = add i32 %lhs, 4094
40 ret i32 %Rd
49 %Rd = add i32 %lhs, 4095
50 ret i32 %Rd
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/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td298 bits<4> Rd;
301 let Inst{11-8} = Rd;
311 bits<4> Rd;
315 let Inst{11-8} = Rd;
337 bits<4> Rd;
340 let Inst{11-8} = Rd;
350 bits<4> Rd;
353 let Inst{11-8} = Rd;
376 bits<4> Rd;
379 let Inst{11-8} = Rd;
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DARMInstrInfo.td1224 let TwoOperandAliasConstraint = "$Rn = $Rd" in
1231 def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm), DPFrm,
1232 iii, opc, "\t$Rd, $Rn, $imm",
1233 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
1235 bits<4> Rd;
1240 let Inst{15-12} = Rd;
1244 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1245 iir, opc, "\t$Rd, $Rn, $Rm",
1246 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
1248 bits<4> Rd;
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DARMInstrThumb.td349 // ADD <Rd>, sp, #<imm8>
815 bits<3> Rd;
817 let Inst{2-0} = Rd;
825 bits<3> Rd;
828 let Inst{2-0} = Rd;
836 bits<3> Rd;
839 let Inst{2-0} = Rd;
845 bits<3> Rd;
848 let Inst{2-0} = Rd;
880 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
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/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td1227 def : InstAlias<asm # "\t$Rd, $imm, $target",
1228 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1275 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1276 [(set regtype:$Rd, (node regtype:$Rn))]>,
1278 bits<5> Rd;
1284 let Inst{4-0} = Rd;
1314 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1315 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1318 bits<5> Rd;
1326 let Inst{4-0} = Rd;
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DAArch64PBQPRegAlloc.cpp159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint() argument
161 if (Rd == Ra) in addIntraChainConstraint()
166 if (TRI->isPhysicalRegister(Rd) || TRI->isPhysicalRegister(Ra)) { in addIntraChainConstraint()
167 DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd) in addIntraChainConstraint()
174 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd); in addIntraChainConstraint()
187 const LiveInterval &ld = LIs.getInterval(Rd); in addIntraChainConstraint()
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint() argument
249 if (Rd != Ra) { in addInterChainConstraint()
251 << PrintReg(Rd, TRI) << '\n';); in addInterChainConstraint()
253 Chains.insert(Rd); in addInterChainConstraint()
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DAArch64PBQPRegAlloc.h31 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
34 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
DAArch64InstrInfo.td450 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
451 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
452 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
453 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
455 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
456 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
457 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
458 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
460 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
461 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
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/external/llvm/lib/Target/Sparc/
DSparcRegisterInfo.td44 // Rd - Slots in the FP register file for 64-bit floating-point values.
45 class Rd<bits<16> Enc, string n, list<Register> subregs> : SparcReg<Enc, n> {
190 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>;
191 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>;
192 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>;
193 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>;
194 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>;
195 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>;
196 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>;
197 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>;
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/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp1834 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
1842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeQADDInstruction()
2037 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2046 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) in DecodeT2MOVTWInstruction()
2048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) in DecodeT2MOVTWInstruction()
2061 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2069 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeArmMOVTWInstruction()
2072 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeArmMOVTWInstruction()
2088 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2097 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) in DecodeSMLAInstruction()
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/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp652 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
657 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
660 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); in DecodeFMOVLaneInstruction()
743 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
771 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
792 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); in DecodeThreeAddrSRegInstruction()
805 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
817 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); in DecodeMoveImmInstruction()
822 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); in DecodeMoveImmInstruction()
1296 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
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/external/vixl/src/vixl/a64/
Dassembler-a64.cc735 Emit(op | (vd.IsQ() ? NEON_Q : 0) | Rm(vm) | Rn(vn) | Rd(vd)); in NEONTable()
873 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr()
884 Emit(ADRP | ImmPCRelAddress(imm21) | Rd(rd)); in adrp()
1055 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
1064 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
1073 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
1082 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1094 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in bfm()
1105 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in sbfm()
1116 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in ubfm()
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Dsimulator-a64.cc817 set_reg(instr->Rd(), instr->ImmPCOffsetTarget()); in VisitPCRelAddressing()
915 set_reg(reg_size, instr->Rd(), new_val, LogRegWrites, instr->RdMode()); in AddSubHelper()
960 set_reg(reg_size, instr->Rd(), new_val); in VisitAddSubWithCarry()
1007 set_reg(reg_size, instr->Rd(), result, LogRegWrites, instr->RdMode()); in LogicalHelper()
1545 unsigned reg_code = instr->Rd(); in VisitMoveWideImmediate()
1562 set_xreg(instr->Rd(), new_xn_val); in VisitMoveWideImmediate()
1584 set_reg(reg_size, instr->Rd(), new_val); in VisitConditionalSelect()
1589 unsigned dst = instr->Rd(); in VisitDataProcessing1Source()
1769 set_reg(reg_size, instr->Rd(), result); in VisitDataProcessing2Source()
1830 set_reg(reg_size, instr->Rd(), result); in VisitDataProcessing3Source()
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/external/v8/src/arm64/
Dassembler-arm64.cc1082 Emit(ADR | ImmPCRelAddress(imm21) | Rd(rd)); in adr()
1252 Emit(SF(rd) | LSLV | Rm(rm) | Rn(rn) | Rd(rd)); in lslv()
1261 Emit(SF(rd) | LSRV | Rm(rm) | Rn(rn) | Rd(rd)); in lsrv()
1270 Emit(SF(rd) | ASRV | Rm(rm) | Rn(rn) | Rd(rd)); in asrv()
1279 Emit(SF(rd) | RORV | Rm(rm) | Rn(rn) | Rd(rd)); in rorv()
1291 Rn(rn) | Rd(rd)); in bfm()
1302 Rn(rn) | Rd(rd)); in sbfm()
1313 Rn(rn) | Rd(rd)); in ubfm()
1323 ImmS(lsb, rn.SizeInBits()) | Rn(rn) | Rd(rd)); in extr()
1398 Emit(SF(rd) | op | Rm(rm) | Cond(cond) | Rn(rn) | Rd(rd)); in ConditionalSelect()
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Dsimulator-arm64.cc909 set_reg<T>(instr->Rd(), new_val); in AddSubWithCarry()
984 set_reg<T>(instr->Rd(), result); in Extract()
1303 set_reg(instr->Rd(), instr->ImmPCOffsetTarget()); in VisitPCRelAddressing()
1412 set_reg<T>(instr->Rd(), new_val, instr->RdMode()); in AddSubHelper()
1513 set_reg<T>(instr->Rd(), result, instr->RdMode()); in LogicalHelper()
1912 unsigned reg_code = instr->Rd(); in VisitMoveWideImmediate()
1928 set_xreg(instr->Rd(), new_xn_val); in VisitMoveWideImmediate()
1956 set_xreg(instr->Rd(), new_val); in VisitConditionalSelect()
1958 set_wreg(instr->Rd(), static_cast<uint32_t>(new_val)); in VisitConditionalSelect()
1964 unsigned dst = instr->Rd(); in VisitDataProcessing1Source()
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/external/mesa3d/src/mesa/swrast/
Ds_blend.c489 const GLfloat Rd = dest[i][RCOMP]; in blend_general_float() local
511 sR = Rd; in blend_general_float()
516 sR = 1.0F - Rd; in blend_general_float()
673 dR = Rd; in blend_general_float()
678 dR = 1.0F - Rd; in blend_general_float()
743 r = Rs * sR + Rd * dR; in blend_general_float()
749 r = Rs * sR - Rd * dR; in blend_general_float()
755 r = Rd * dR - Rs * sR; in blend_general_float()
761 r = MIN2( Rd, Rs ); in blend_general_float()
766 r = MAX2( Rd, Rs ); in blend_general_float()
/external/valgrind/none/tests/arm/
Dvfp.stdout.exp77 vmov.32 r5, d0[0] :: Rd 0x7fc00000 Qm (i32)0x7fc00000
78 vmov.32 r6, d5[1] :: Rd 0x7f800000 Qm (i32)0x7f800000
79 vmov.32 r4, d10[0] :: Rd 0xff800000 Qm (i32)0xff800000
80 vmov.32 r5, d15[1] :: Rd 0x11223344 Qm (i32)0x11223344
81 vmov.32 r9, d20[0] :: Rd 0x11223344 Qm (i32)0x11223344
82 vmov.32 r8, d25[1] :: Rd 0x11223344 Qm (i32)0x11223344
83 vmov.32 r0, d30[0] :: Rd 0x11223344 Qm (i32)0x11223344
84 vmov.32 r2, d19[1] :: Rd 0x11223344 Qm (i32)0x11223344
85 vmov.u16 r5, d31[0] :: Rd 0x00000000 Qm (i32)0x7fc00000
86 vmov.u16 r3, d30[1] :: Rd 0x00007f80 Qm (i32)0x7f800000
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