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Searched refs:addReg (Results 1 – 25 of 134) sorted by relevance

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/external/llvm/lib/Target/R600/
DSILowerControlFlow.cpp143 .addReg(AMDGPU::EXEC); in Skip()
162 .addReg(AMDGPU::EXEC); in SkipIfDead()
171 .addReg(AMDGPU::VGPR0) in SkipIfDead()
172 .addReg(AMDGPU::VGPR0) in SkipIfDead()
173 .addReg(AMDGPU::VGPR0) in SkipIfDead()
174 .addReg(AMDGPU::VGPR0); in SkipIfDead()
187 .addReg(Vcc); in If()
190 .addReg(AMDGPU::EXEC) in If()
191 .addReg(Reg); in If()
206 .addReg(Src); // Saved EXEC in Else()
[all …]
DSIPrepareScratchRegs.cpp96 .addReg(ScratchOffsetPreloadReg); in runOnMachineFunction()
101 .addReg(ScratchOffsetPreloadReg) in runOnMachineFunction()
103 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in runOnMachineFunction()
104 .addReg(AMDGPU::SGPR0, RegState::Undef); in runOnMachineFunction()
159 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
163 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
167 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
171 .addReg(ScratchRsrcReg, RegState::ImplicitDefine); in runOnMachineFunction()
179 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in runOnMachineFunction()
180 .addReg(AMDGPU::SGPR0, RegState::Undef); in runOnMachineFunction()
DSIInstrInfo.cpp339 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
346 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
352 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
360 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
382 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
422 Builder.addReg(RI.getSubReg(SrcReg, SubIdx), getKillRegState(KillSrc)); in copyPhysReg()
425 Builder.addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
500 .addReg(SrcReg) in storeRegToStackSlot()
504 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in storeRegToStackSlot()
505 .addReg(AMDGPU::SGPR0, RegState::Undef); in storeRegToStackSlot()
[all …]
/external/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp135 .addReg(ThumbIndirectPads[i].first) in runOnMachineFunction()
138 .addReg(0)); in runOnMachineFunction()
1015 .addReg(0)); in EmitJump2Table()
1221 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1225 .addReg(MI->getOperand(3).getReg())); in EmitInstruction()
1238 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
1242 .addReg(MI->getOperand(4).getReg())); in EmitInstruction()
1249 .addReg(ARM::LR) in EmitInstruction()
1250 .addReg(ARM::PC) in EmitInstruction()
1253 .addReg(0) in EmitInstruction()
[all …]
DARMFrameLowering.cpp250 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
255 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
264 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
268 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
276 .addReg(Reg, RegState::Kill) in emitAligningInstructions()
454 .addImm((unsigned)ARMCC::AL).addReg(0) in emitPrologue()
456 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
466 .addImm((unsigned)ARMCC::AL).addReg(0) in emitPrologue()
467 .addReg(ARM::R12, RegState::Kill) in emitPrologue()
468 .addReg(ARM::R4, RegState::Implicit) in emitPrologue()
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DARMLoadStoreOptimizer.cpp450 .addReg(Base, getKillRegState(false)).addImm(WordOffset * 4) in UpdateBaseRegUses()
451 .addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
469 .addReg(Base, getKillRegState(false)).addImm(WordOffset * 4) in UpdateBaseRegUses()
470 .addImm(Pred).addReg(PredReg); in UpdateBaseRegUses()
586 .addReg(Base, getKillRegState(BaseKill)); in MergeOps()
589 .addReg(Base, getKillRegState(BaseKill)) in MergeOps()
590 .addImm(Pred).addReg(PredReg); in MergeOps()
599 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset/4) in MergeOps()
600 .addImm(Pred).addReg(PredReg); in MergeOps()
603 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset) in MergeOps()
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DARMExpandPseudoInsts.cpp397 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
399 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
401 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
403 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
434 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
472 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); in ExpandVST()
474 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); in ExpandVST()
476 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); in ExpandVST()
478 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); in ExpandVST()
487 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. in ExpandVST()
[all …]
DARMFastISel.cpp297 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
300 .addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
303 .addReg(II.ImplicitDefs[0])); in fastEmitInst_r()
323 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
324 .addReg(Op1, Op1IsKill * RegState::Kill)); in fastEmitInst_rr()
327 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rr()
328 .addReg(Op1, Op1IsKill * RegState::Kill)); in fastEmitInst_rr()
331 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rr()
353 .addReg(Op0, Op0IsKill * RegState::Kill) in fastEmitInst_rrr()
354 .addReg(Op1, Op1IsKill * RegState::Kill) in fastEmitInst_rrr()
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DThumb2InstrInfo.cpp121 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
144 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
204 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
227 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
228 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
245 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
250 .addReg(DestReg) in emitT2RegPlusImmediate()
252 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
259 .addReg(BaseReg, RegState::Kill) in emitT2RegPlusImmediate()
260 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
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/external/llvm/lib/Target/X86/
DX86InstrBuilder.h94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
128 MIB.addReg(AM.Base.Reg); in addFullAddress()
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg); in addFullAddress()
140 return MIB.addReg(0); in addFullAddress()
178 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0) in addConstantPoolReference()
179 .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0); in addConstantPoolReference()
DX86FrameLowering.cpp245 .addReg(StackPtr) in emitSPUpdate()
246 .addReg(Reg); in emitSPUpdate()
264 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); in emitSPUpdate()
279 .addReg(StackPtr) in emitSPUpdate()
432 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11); in emitStackProbeCall()
439 CI.addReg(AX, RegState::Implicit) in emitStackProbeCall()
440 .addReg(SP, RegState::Implicit) in emitStackProbeCall()
441 .addReg(AX, RegState::Define | RegState::Implicit) in emitStackProbeCall()
442 .addReg(SP, RegState::Define | RegState::Implicit) in emitStackProbeCall()
443 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); in emitStackProbeCall()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
61 .addReg(MI->getOperand(0).getReg()) in lowerRIEfLow()
62 .addReg(MI->getOperand(1).getReg()) in lowerRIEfLow()
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) in lowerRIEfLow()
88 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D); in EmitInstruction()
[all …]
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmInstrumentation.cpp520 EmitInstruction(Out, MCInstBuilder(X86::PUSH32r).addReg(Reg)); in SpillReg()
525 EmitInstruction(Out, MCInstBuilder(X86::POP32r).addReg(Reg)); in RestoreReg()
556 MCInstBuilder(X86::MOV32rr).addReg(LocalFrameReg).addReg(FrameReg)); in InstrumentMemOperandPrologue()
610 .addReg(X86::ESP) in EmitCallAsanReport()
611 .addReg(X86::ESP) in EmitCallAsanReport()
614 Out, MCInstBuilder(X86::PUSH32r).addReg(RegCtx.AddressReg(MVT::i32))); in EmitCallAsanReport()
636 EmitInstruction(Out, MCInstBuilder(X86::MOV32rr).addReg(ShadowRegI32).addReg( in InstrumentMemOperandSmall()
639 .addReg(ShadowRegI32) in InstrumentMemOperandSmall()
640 .addReg(ShadowRegI32) in InstrumentMemOperandSmall()
656 Out, MCInstBuilder(X86::TEST8rr).addReg(ShadowRegI8).addReg(ShadowRegI8)); in InstrumentMemOperandSmall()
[all …]
/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp151 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); in emitInstStore()
155 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); in emitInstLoad()
251 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
274 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
277 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
286 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); in materialize32BitInt()
301 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
309 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); in materializeFP()
327 .addReg(MFI->getGlobalBaseReg()) in materializeGV()
333 .addReg(DestReg) in materializeGV()
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DMipsLongBranch.cpp232 MIB.addReg(MO.getReg()); in replaceBranch()
297 .addReg(Mips::SP).addImm(-8); in expandToLongBranch()
298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) in expandToLongBranch()
299 .addReg(Mips::SP).addImm(0); in expandToLongBranch()
322 .addReg(Mips::AT) in expandToLongBranch()
329 .addReg(Mips::RA).addReg(Mips::AT); in expandToLongBranch()
331 .addReg(Mips::SP).addImm(0); in expandToLongBranch()
335 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT)) in expandToLongBranch()
337 .addReg(Mips::SP).addImm(8)); in expandToLongBranch()
341 .addReg(Mips::SP).addImm(8); in expandToLongBranch()
[all …]
DMipsSEInstrInfo.cpp108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) in copyPhysReg()
130 .addReg(DestReg, RegState::ImplicitDefine); in copyPhysReg()
170 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
173 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
176 MIB.addReg(ZeroReg); in copyPhysReg()
218 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
371 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); in adjustStackPtr()
374 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); in adjustStackPtr()
408 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) in loadImmediate()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp72 .addReg(FrameReg) in InsertFPImmInst()
78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
79 .addReg(FrameReg) in InsertFPImmInst()
85 .addReg(FrameReg) in InsertFPImmInst()
108 .addReg(FrameReg) in InsertFPConstInst()
109 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
115 .addReg(FrameReg) in InsertFPConstInst()
116 .addReg(ScratchOffset, RegState::Kill) in InsertFPConstInst()
121 .addReg(FrameReg) in InsertFPConstInst()
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/external/llvm/lib/Target/Hexagon/
DHexagonExpandPredSpillCode.cpp258 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1); in runOnMachineFunction()
260 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
263 .addReg(HEXAGON_RESERVED_REG_1) in runOnMachineFunction()
264 .addImm(0).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
267 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); in runOnMachineFunction()
269 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
272 .addReg(HEXAGON_RESERVED_REG_1) in runOnMachineFunction()
274 .addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
278 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
281 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp353 .addReg(SrcReg) in HandleVRSaveUpdate()
357 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
362 .addReg(SrcReg) in HandleVRSaveUpdate()
366 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
371 .addReg(SrcReg) in HandleVRSaveUpdate()
375 .addReg(SrcReg, RegState::Kill) in HandleVRSaveUpdate()
379 .addReg(DstReg, RegState::Kill) in HandleVRSaveUpdate()
701 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill); in emitPrologue()
707 .addReg(FPReg) in emitPrologue()
709 .addReg(SPReg); in emitPrologue()
[all …]
DPPCAsmPrinter.cpp375 .addReg(ScratchReg) in LowerPATCHPOINT()
378 .addReg(ScratchReg) in LowerPATCHPOINT()
379 .addReg(ScratchReg) in LowerPATCHPOINT()
382 .addReg(ScratchReg) in LowerPATCHPOINT()
383 .addReg(ScratchReg) in LowerPATCHPOINT()
386 .addReg(ScratchReg) in LowerPATCHPOINT()
387 .addReg(ScratchReg) in LowerPATCHPOINT()
390 EmitToStreamer(OutStreamer, MCInstBuilder(PPC::MTCTR8).addReg(ScratchReg)); in LowerPATCHPOINT()
735 .addReg(MI->getOperand(0).getReg()) in EmitInstruction()
736 .addReg(MI->getOperand(1).getReg()) in EmitInstruction()
[all …]
DPPCRegisterInfo.cpp358 .addReg(PPC::R31) in lowerDynamicAlloc()
363 .addReg(PPC::X1); in lowerDynamicAlloc()
367 .addReg(PPC::R1); in lowerDynamicAlloc()
388 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in lowerDynamicAlloc()
389 .addReg(NegSizeReg1, RegState::Kill); in lowerDynamicAlloc()
394 .addReg(Reg, RegState::Kill) in lowerDynamicAlloc()
395 .addReg(PPC::X1) in lowerDynamicAlloc()
396 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
398 .addReg(PPC::X1) in lowerDynamicAlloc()
413 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in lowerDynamicAlloc()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DR600InstrInfo.cpp59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) in copyPhysReg()
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex)) in copyPhysReg()
62 .addReg(0) // PREDICATE_BIT in copyPhysReg()
63 .addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
72 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
74 .addReg(0); // PREDICATE_BIT in copyPhysReg()
82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); in getMovImmInstr()
83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X); in getMovImmInstr()
85 MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT in getMovImmInstr()
271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0); in InsertBranch()
[all …]
DR600ISelLowering.cpp69 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
80 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
92 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
103 .addReg(ConstantReg); in EmitInstrWithCustomInserter()
131 .addReg(AMDGPU::ALU_LITERAL_X) in EmitInstrWithCustomInserter()
132 .addReg(AMDGPU::PRED_SEL_OFF) in EmitInstrWithCustomInserter()
136 .addReg(ShiftValue) in EmitInstrWithCustomInserter()
137 .addReg(AMDGPU::PRED_SEL_OFF); in EmitInstrWithCustomInserter()
140 .addReg(NewAddr) in EmitInstrWithCustomInserter()
173 .addReg(t0, RegState::Implicit) in EmitInstrWithCustomInserter()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp101 .addReg(AArch64::XZR) in tryOrrMovk()
110 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryOrrMovk()
111 .addReg(DstReg) in tryOrrMovk()
168 .addReg(AArch64::XZR) in tryToreplicateChunks()
187 .addReg(DstReg, in tryToreplicateChunks()
189 .addReg(DstReg) in tryToreplicateChunks()
212 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in tryToreplicateChunks()
213 .addReg(DstReg) in tryToreplicateChunks()
351 .addReg(AArch64::XZR) in trySequenceOfOnes()
361 .addReg(DstReg, in trySequenceOfOnes()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430FrameLowering.cpp68 .addReg(MSP430::FP, RegState::Kill); in emitPrologue()
72 .addReg(MSP430::SP); in emitPrologue()
100 .addReg(MSP430::SP).addImm(NumBytes); in emitPrologue()
158 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP); in emitEpilogue()
163 .addReg(MSP430::SP).addImm(CSSize); in emitEpilogue()
172 .addReg(MSP430::SP).addImm(NumBytes); in emitEpilogue()
201 .addReg(Reg, RegState::Kill); in spillCalleeSavedRegisters()
250 .addReg(MSP430::SP).addImm(Amount); in eliminateCallFramePseudoInstr()
259 .addReg(MSP430::SP).addImm(Amount); in eliminateCallFramePseudoInstr()
277 MSP430::SP).addReg(MSP430::SP).addImm(CalleeAmt); in eliminateCallFramePseudoInstr()

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