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Searched refs:ISD (Results 1 – 25 of 149) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp36 if (getOpcode() < ISD::BUILTIN_OP_END) in getOperationName()
54 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; in getOperationName()
56 case ISD::PREFETCH: return "Prefetch"; in getOperationName()
57 case ISD::ATOMIC_FENCE: return "AtomicFence"; in getOperationName()
58 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; in getOperationName()
59 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: return "AtomicCmpSwapWithSuccess"; in getOperationName()
60 case ISD::ATOMIC_SWAP: return "AtomicSwap"; in getOperationName()
61 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; in getOperationName()
62 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; in getOperationName()
63 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; in getOperationName()
[all …]
DLegalizeVectorOps.cpp199 if (Op.getOpcode() == ISD::LOAD) { in LegalizeOp()
201 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
228 } else if (Op.getOpcode() == ISD::STORE) { in LegalizeOp()
260 case ISD::ADD: in LegalizeOp()
261 case ISD::SUB: in LegalizeOp()
262 case ISD::MUL: in LegalizeOp()
263 case ISD::SDIV: in LegalizeOp()
264 case ISD::UDIV: in LegalizeOp()
265 case ISD::SREM: in LegalizeOp()
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DLegalizeIntegerTypes.cpp52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; in PromoteIntegerResult()
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; in PromoteIntegerResult()
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; in PromoteIntegerResult()
59 case ISD::CONVERT_RNDSAT: in PromoteIntegerResult()
61 case ISD::CTLZ_ZERO_UNDEF: in PromoteIntegerResult()
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
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DLegalizeDAG.cpp263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) && in ExpandConstantFP()
276 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, in ExpandConstantFP()
293 assert(ST->getAddressingMode() == ISD::UNINDEXED && in ExpandUnalignedStore()
310 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); in ExpandUnalignedStore()
351 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, in ExpandUnalignedStore()
353 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); in ExpandUnalignedStore()
363 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, in ExpandUnalignedStore()
375 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores); in ExpandUnalignedStore()
391 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
399 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, in ExpandUnalignedStore()
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DTargetLowering.cpp122 ISD::CondCode &CCCode, in softenSetCCOperands()
130 case ISD::SETEQ: in softenSetCCOperands()
131 case ISD::SETOEQ: in softenSetCCOperands()
135 case ISD::SETNE: in softenSetCCOperands()
136 case ISD::SETUNE: in softenSetCCOperands()
140 case ISD::SETGE: in softenSetCCOperands()
141 case ISD::SETOGE: in softenSetCCOperands()
145 case ISD::SETLT: in softenSetCCOperands()
146 case ISD::SETOLT: in softenSetCCOperands()
150 case ISD::SETLE: in softenSetCCOperands()
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DDAGCombiner.cpp136 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
213 ISD::NodeType ExtType);
321 SDValue N3, ISD::CondCode CC,
323 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
519 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
529 case ISD::ConstantFP: in isNegatibleForFree()
533 case ISD::FADD: in isNegatibleForFree()
539 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) in isNegatibleForFree()
549 case ISD::FSUB: in isNegatibleForFree()
556 case ISD::FMUL: in isNegatibleForFree()
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DLegalizeVectorTypes.cpp51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
54 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; in ScalarizeVectorResult()
55 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
57 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; in ScalarizeVectorResult()
58 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; in ScalarizeVectorResult()
59 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
60 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; in ScalarizeVectorResult()
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DSelectionDAG.cpp97 bool ISD::isBuildVectorAllOnes(const SDNode *N) { in isBuildVectorAllOnes()
99 while (N->getOpcode() == ISD::BITCAST) in isBuildVectorAllOnes()
102 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllOnes()
107 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) in isBuildVectorAllOnes()
137 N->getOperand(i).getOpcode() != ISD::UNDEF) in isBuildVectorAllOnes()
145 bool ISD::isBuildVectorAllZeros(const SDNode *N) { in isBuildVectorAllZeros()
147 while (N->getOpcode() == ISD::BITCAST) in isBuildVectorAllZeros()
150 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllZeros()
154 if (N->getOperand(i).getOpcode() == ISD::UNDEF) in isBuildVectorAllZeros()
185 bool ISD::isBuildVectorOfConstantSDNodes(const SDNode *N) { in isBuildVectorOfConstantSDNodes()
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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp51 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
52 assert(ISD && "Invalid opcode"); in getCastInstrCost()
57 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
58 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
59 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
62 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
63 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
65 int Idx = CostTableLookup(NEONFltDblTbl, ISD, LT.second); in getCastInstrCost()
81 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
82 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
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DARMISelLowering.cpp96 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
99 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
105 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
109 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
110 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForNEON()
111 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp88 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
89 assert(ISD && "Invalid opcode"); in getArithmeticInstrCost()
91 if (ISD == ISD::SDIV && in getArithmeticInstrCost()
114 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence in getArithmeticInstrCost()
115 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence in getArithmeticInstrCost()
116 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence in getArithmeticInstrCost()
117 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence in getArithmeticInstrCost()
122 int Idx = CostTableLookup(AVX2UniformConstCostTable, ISD, LT.second); in getArithmeticInstrCost()
128 { ISD::SHL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
129 { ISD::SRL, MVT::v16i32, 1 }, in getArithmeticInstrCost()
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DX86ISelLowering.cpp157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in X86TargetLowering()
170 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); in X86TargetLowering()
171 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); in X86TargetLowering()
172 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); in X86TargetLowering()
173 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); in X86TargetLowering()
174 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); in X86TargetLowering()
175 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); in X86TargetLowering()
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); in X86TargetLowering()
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); in X86TargetLowering()
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); in X86TargetLowering()
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/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp110 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); in InitAMDILLowering()
111 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
112 setOperationAction(ISD::SUBC, VT, Expand); in InitAMDILLowering()
113 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
114 setOperationAction(ISD::ADDC, VT, Expand); in InitAMDILLowering()
115 setOperationAction(ISD::BRCOND, VT, Custom); in InitAMDILLowering()
116 setOperationAction(ISD::BR_JT, VT, Expand); in InitAMDILLowering()
117 setOperationAction(ISD::BRIND, VT, Expand); in InitAMDILLowering()
119 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
120 setOperationAction(ISD::SMUL_LOHI, VT, Expand); in InitAMDILLowering()
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DAMDGPUISelLowering.cpp31 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
35 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
37 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
39 setOperationAction(ISD::UDIV, MVT::i32, Expand); in AMDGPUTargetLowering()
40 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); in AMDGPUTargetLowering()
41 setOperationAction(ISD::UREM, MVT::i32, Expand); in AMDGPUTargetLowering()
52 const SmallVectorImpl<ISD::InputArg> &Ins, in LowerFormalArguments()
68 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
89 case ISD::SDIV: return LowerSDIV(Op, DAG); in LowerOperation()
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/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp76 ISD::ArgFlagsTy ArgFlags, CCState &State) { in allocateStack()
108 setOperationAction(ISD::Constant, MVT::i32, Legal); in AMDGPUTargetLowering()
109 setOperationAction(ISD::Constant, MVT::i64, Legal); in AMDGPUTargetLowering()
110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); in AMDGPUTargetLowering()
111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); in AMDGPUTargetLowering()
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in AMDGPUTargetLowering()
114 setOperationAction(ISD::BRIND, MVT::Other, Expand); in AMDGPUTargetLowering()
117 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
121 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
122 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
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DSIISelLowering.cpp65 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); in SITargetLowering()
66 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); in SITargetLowering()
67 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering()
68 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
70 setOperationAction(ISD::ADD, MVT::i32, Legal); in SITargetLowering()
71 setOperationAction(ISD::ADDC, MVT::i32, Legal); in SITargetLowering()
72 setOperationAction(ISD::ADDE, MVT::i32, Legal); in SITargetLowering()
73 setOperationAction(ISD::SUBC, MVT::i32, Legal); in SITargetLowering()
74 setOperationAction(ISD::SUBE, MVT::i32, Legal); in SITargetLowering()
76 setOperationAction(ISD::FSIN, MVT::f32, Custom); in SITargetLowering()
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DR600ISelLowering.cpp46 setCondCodeAction(ISD::SETO, MVT::f32, Expand); in R600TargetLowering()
47 setCondCodeAction(ISD::SETUO, MVT::f32, Expand); in R600TargetLowering()
48 setCondCodeAction(ISD::SETLT, MVT::f32, Expand); in R600TargetLowering()
49 setCondCodeAction(ISD::SETLE, MVT::f32, Expand); in R600TargetLowering()
50 setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); in R600TargetLowering()
51 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); in R600TargetLowering()
52 setCondCodeAction(ISD::SETONE, MVT::f32, Expand); in R600TargetLowering()
53 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); in R600TargetLowering()
54 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); in R600TargetLowering()
55 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); in R600TargetLowering()
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp67 ISD::ArgFlagsTy ArgFlags, CCState &State);
72 ISD::ArgFlagsTy ArgFlags, CCState &State);
77 ISD::ArgFlagsTy ArgFlags, CCState &State);
82 ISD::ArgFlagsTy ArgFlags, CCState &State);
87 ISD::ArgFlagsTy ArgFlags, CCState &State);
92 ISD::ArgFlagsTy ArgFlags, CCState &State);
97 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon_VarArg()
147 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon()
191 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon32()
209 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon64()
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/external/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.cpp181 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
182 assert(ISD && "Invalid opcode"); in getCastInstrCost()
192 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
193 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
194 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
195 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
196 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
197 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
200 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
201 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
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DAArch64ISelLowering.cpp125 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in AArch64TargetLowering()
126 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); in AArch64TargetLowering()
127 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
128 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
129 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
130 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
131 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in AArch64TargetLowering()
132 setOperationAction(ISD::BR_CC, MVT::i32, Custom); in AArch64TargetLowering()
133 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in AArch64TargetLowering()
134 setOperationAction(ISD::BR_CC, MVT::f32, Custom); in AArch64TargetLowering()
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/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp81 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
82 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
86 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
87 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); in MSP430TargetLowering()
88 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); in MSP430TargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); in MSP430TargetLowering()
95 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
96 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
97 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
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/external/llvm/include/llvm/CodeGen/
DBasicTTIImpl.h188 return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || in shouldBuildLookupTables()
189 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other); in shouldBuildLookupTables()
196 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
298 int ISD = TLI->InstructionOpcodeToISD(Opcode); variable
299 assert(ISD && "Invalid opcode");
308 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) {
318 if (!TLI->isOperationExpand(ISD, LT.second)) {
349 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
350 assert(ISD && "Invalid opcode"); in getCastInstrCost()
374 TLI->isOperationLegalOrPromote(ISD, DstLT.second)) in getCastInstrCost()
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/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp41 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
54 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_f64()
83 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Full()
128 ISD::ArgFlagsTy &ArgFlags, CCState &State) { in CC_Sparc64_Half()
173 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
184 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_32()
246 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_64()
276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
282 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
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/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp103 setOperationAction(ISD::BR_CC, MVT::i64, Custom); in BPFTargetLowering()
104 setOperationAction(ISD::BR_JT, MVT::Other, Expand); in BPFTargetLowering()
105 setOperationAction(ISD::BRCOND, MVT::Other, Expand); in BPFTargetLowering()
106 setOperationAction(ISD::SETCC, MVT::i64, Expand); in BPFTargetLowering()
107 setOperationAction(ISD::SELECT, MVT::i64, Expand); in BPFTargetLowering()
108 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); in BPFTargetLowering()
110 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); in BPFTargetLowering()
112 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); in BPFTargetLowering()
113 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); in BPFTargetLowering()
114 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in BPFTargetLowering()
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/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp52 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
53 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
54 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
66 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) in MipsSETargetLowering()
69 setOperationAction(ISD::ADD, VecTys[i], Legal); in MipsSETargetLowering()
70 setOperationAction(ISD::SUB, VecTys[i], Legal); in MipsSETargetLowering()
71 setOperationAction(ISD::LOAD, VecTys[i], Legal); in MipsSETargetLowering()
72 setOperationAction(ISD::STORE, VecTys[i], Legal); in MipsSETargetLowering()
73 setOperationAction(ISD::BITCAST, VecTys[i], Legal); in MipsSETargetLowering()
76 setTargetDAGCombine(ISD::SHL); in MipsSETargetLowering()
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